IBM PPC440X5 Manual de usuario

PPC440x5 CPU CoreUser’s Manual PreliminarySA14-2613-02September 12, 2002Title Page

User’s ManualPPC440x5 CPU Core PreliminaryPage 10 of 583ppc440x5TOC.fm.September 12, 2002icbt...

User’s ManualPPC440x5 CPU Core PreliminaryPage 100 of 589cache.fm.September 12, 2002Replacement Policy on page 96, the values of the fields are constr

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 101 of 589block -- 32 bytes), it takes sixteen such dcbt operations (one for

User’s ManualPPC440x5 CPU Core PreliminaryPage 102 of 589cache.fm.September 12, 2002Figure 4-3 and Figure 4-4 illustrate two of these examples of the

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 103 of 5894.2 Instruction Cache ControllerThe instruction cache controller (

User’s ManualPPC440x5 CPU Core PreliminaryPage 104 of 589cache.fm.September 12, 2002The ICC also handles the execution of the PowerPC instruction cach

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 105 of 589the ICC will immediately present the request for the new cache lin

User’s ManualPPC440x5 CPU Core PreliminaryPage 106 of 589cache.fm.September 12, 2002lines beyond the one in progress at the time that the ICC determin

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 107 of 589At this point, software may begin executing the instruction at add

User’s ManualPPC440x5 CPU Core PreliminaryPage 108 of 589cache.fm.September 12, 2002Alternatively, software can execute an iccci instruction, which fl

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 109 of 589Figure 4-5. Core Configuration Register 0 (CCR0)0 Reserved1 PREPari

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5TOC.fm.September 12, 2002Page 11 of 583mtspr ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 110 of 589cache.fm.September 12, 20024.2.4.3 Core Configuration Register 1 (CCR1)The CCR1 register contr

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 111 of 5894.2.4.4 icbt OperationThe icbt instruction is typically used as a

User’s ManualPPC440x5 CPU Core PreliminaryPage 112 of 589cache.fm.September 12, 2002When being used for these latter purposes, it is important that th

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 113 of 589mficdbdr regC # move instruction information into GPR Cmficdbtrh reg

User’s ManualPPC440x5 CPU Core PreliminaryPage 114 of 589cache.fm.September 12, 20024.2.4.6 Instruction Cache Parity OperationsThe instruction cache c

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 115 of 589There are 10 parity bits stored in the RAM cells of each instructi

User’s ManualPPC440x5 CPU Core PreliminaryPage 116 of 589cache.fm.September 12, 2002support direct attachment to 32-bit and 64-bit PLB subsystems, as

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 117 of 589Once a data cache line read request has been made, the entire line

User’s ManualPPC440x5 CPU Core PreliminaryPage 118 of 589cache.fm.September 12, 2002The load and store string and multiple instructions are performed

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 119 of 5894.3.1.3 Store OperationsThe processing of store instructions in th

User’s ManualPPC440x5 CPU Core PreliminaryPage 12 of 583ppc440x5TOC.fm.September 12, 2002stwu ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 120 of 589cache.fm.September 12, 2002A given sequence of two store operations may only be gathered toge

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 121 of 589Table 4-5 summarizes how the various storage attributes and other

User’s ManualPPC440x5 CPU Core PreliminaryPage 122 of 589cache.fm.September 12, 2002set instead of just the one corresponding dirty bit). When a data

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 123 of 5894.3.1.6 Data Write PLB Interface RequestsWhen a PLB write request

User’s ManualPPC440x5 CPU Core PreliminaryPage 124 of 589cache.fm.September 12, 20024.3.1.7 Storage Access OrderingIn general, the DCC can perform loa

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 125 of 5894.3.3 Data Cache Control and DebugThe PPC440x5 core provides vario

User’s ManualPPC440x5 CPU Core PreliminaryPage 126 of 589cache.fm.September 12, 20024.3.3.2 Core Configuration Register 0 (CCR0)The CCR0 register contr

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 127 of 589the specified cache line in the data cache (assuming that a TLB en

User’s ManualPPC440x5 CPU Core PreliminaryPage 128 of 589cache.fm.September 12, 2002The following figures illustrate the DCDBTRH and DCDBTRL.Figure 4-

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 129 of 5894.3.3.6 Data Cache Parity OperationsThe data cache contains parity

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5TOC.fm.September 12, 2002Page 13 of 583ICDBDR...

User’s ManualPPC440x5 CPU Core PreliminaryPage 130 of 589cache.fm.September 12, 2002MCSR[DCSP] and MCSR[DCFP] indicate what type of data cache operati

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 131 of 589If the CCR1[DCMPEI] bit is set, the parity for any modified (dirty

User’s ManualPPC440x5 CPU Core PreliminaryPage 132 of 589cache.fm.September 12, 2002

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 133 of 5895. Memory ManagementThe PPC440x5 supports a uniform, 4 gigabyte (GB)

User’s ManualPPC440x5 CPU Core PreliminaryPage 134 of 589mmu.fm.September 12, 2002• Memory coherence required (M) storage attributeBecause the PPC440x

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 135 of 589Maintenance of TLB entries is under software control. System softwar

User’s ManualPPC440x5 CPU Core PreliminaryPage 136 of 589mmu.fm.September 12, 2002Address Translation Fields1 0:21 RPNReal Page Number (variable size,

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 137 of 589222MMemory Coherence Required (1 bit) See Memory Coherence Required

User’s ManualPPC440x5 CPU Core PreliminaryPage 138 of 589mmu.fm.September 12, 20025.3 Page IdentificationThe Valid (V), Effective Page Number (EPN), Tr

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 139 of 589space, allowing user mode programs running with MSR[IS,DS] set to 1

User’s ManualPPC440x5 CPU Core PreliminaryPage 14 of 583ppc440x5TOC.fm.September 12, 2002Index ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 140 of 589mmu.fm.September 12, 2002Figure 5-1 illustrates the criteria for a virtual address to match a

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 141 of 589The Real Page Number (RPN) and Extended Real Page Number (ERPN) fiel

User’s ManualPPC440x5 CPU Core PreliminaryPage 142 of 589mmu.fm.September 12, 20025.5 Access ControlOnce a matching TLB entry has been identified and

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 143 of 589store operation is attempted in user mode to a page for which the UW

User’s ManualPPC440x5 CPU Core PreliminaryPage 144 of 589mmu.fm.September 12, 2002• dcbz instructions are treated as stores with respect to access con

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 145 of 5895.6 Storage AttributesEach TLB entry specifies a number of storage a

User’s ManualPPC440x5 CPU Core PreliminaryPage 146 of 589mmu.fm.September 12, 2002See Instruction and Data Caches on page 95 for more information on t

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 147 of 589which means that the bytes are arranged with the most-significant by

User’s ManualPPC440x5 CPU Core PreliminaryPage 148 of 589mmu.fm.September 12, 20025.7.1 Memory Management Unit Control Register (MMUCR)The MMUCR is wr

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 149 of 589Store Without Allocate (SWOA) FieldPerformance for certain applicati

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5LOF.fm.September 12, 2002Page 15 of 583FiguresFigure 1-1. PPC440 Core Block Diagram ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 150 of 589mmu.fm.September 12, 2002program to remove a locked line from the cache. The locking and unlo

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 151 of 589Search Translation ID (STID) FieldThe STID field is used by the tlbs

User’s ManualPPC440x5 CPU Core PreliminaryPage 152 of 589mmu.fm.September 12, 2002The instruction shadow TLB (ITLB) contains four entries, while the d

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 153 of 589is the Data Exception Address Register (DEAR), which provides the ex

User’s ManualPPC440x5 CPU Core PreliminaryPage 154 of 589mmu.fm.September 12, 20025.9.3 TLB Sync Instruction (tlbsync)The tlbsync instruction is used

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 155 of 589Execute, Read and Write Access Control exceptions may be used to all

User’s ManualPPC440x5 CPU Core PreliminaryPage 156 of 589mmu.fm.September 12, 20022. MSR[ME] = 1, so the CPU vectors to the machine check handler (i.e

User’s ManualPreliminary PPC440x5 CPU Coremmu.fm.September 12, 2002Page 157 of 589tlbwe Rs,Ra,2 ; write some data to the TLB with bad parityisync ; wa

User’s ManualPPC440x5 CPU Core PreliminaryPage 158 of 589mmu.fm.September 12, 2002

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 159 of 5896. Interrupts and ExceptionsThis chapter begins by defining the

User’s ManualPPC440x5 CPU Core PreliminaryPage 16 of 583ppc440x5LOF.fm.September 12, 2002Figure 6-3. Save/Restore Register 1 (SRR1) ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 160 of 589intrupts.fm.September 12, 2002Synchronous, precise interrupts are those that precisely indica

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 161 of 589• No instruction following the instruction addressed by SRR0 or

User’s ManualPPC440x5 CPU Core PreliminaryPage 162 of 589intrupts.fm.September 12, 2002properly be classified as either synchronous or asynchronous, n

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 163 of 589Interrupt processing consists of saving a small part of the pro

User’s ManualPPC440x5 CPU Core PreliminaryPage 164 of 589intrupts.fm.September 12, 20026.3.1 Partially Executed InstructionsIn general, the architectu

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 165 of 589DecrementerFixed-Interval TimerWatchdog TimerDebug (Uncondition

User’s ManualPPC440x5 CPU Core PreliminaryPage 166 of 589intrupts.fm.September 12, 200214 CECritical Interrupt Enable0 Critical Input and Watchdog Tim

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 167 of 5896.4.2 Save/Restore Register 0 (SRR0)SRR0 is an SPR that is used

User’s ManualPPC440x5 CPU Core PreliminaryPage 168 of 589intrupts.fm.September 12, 20026.4.4 Critical Save/Restore Register 0 (CSRR0)CSRR0 is an SPR t

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 169 of 589Programming Note: An MSR bit that is reserved may be altered by

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5LOF.fm.September 12, 2002Page 17 of 583Figure 10-14. Data Cache Debug Tag Register Low (DCDBTRL) ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 170 of 589intrupts.fm.September 12, 2002Programming Note: An MSR bit that is reserved may be altered by

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 171 of 589Figure 6-8 shows the IVOR field definitions, while Table 6-1 id

User’s ManualPPC440x5 CPU Core PreliminaryPage 172 of 589intrupts.fm.September 12, 20026.4.11 Exception Syndrome Register (ESR)The ESR provides a synd

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 173 of 5897 FPFloating Point Operation0 Exception was not caused by a floa

User’s ManualPPC440x5 CPU Core PreliminaryPage 174 of 589intrupts.fm.September 12, 20026.4.12 Machine Check Status Register (MCSR)The MCSR contains st

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 175 of 5896.5 Interrupt DefinitionsTable 6-2 provides a summary of each in

User’s ManualPPC440x5 CPU Core PreliminaryPage 176 of 589intrupts.fm.September 12, 2002IVOR6 ProgramIllegal Instruction x PILPrivileged Instruction x

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 177 of 589Table Notes1. Although it is not specified as part of Book E, it

User’s ManualPPC440x5 CPU Core PreliminaryPage 178 of 589intrupts.fm.September 12, 20026.5.1 Critical Input InterruptA Critical Input interrupt occurs

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 179 of 589tion, regardless of the state of the MSR[ME] bit.If MSR[ME] is

User’s ManualPPC440x5 CPU Core PreliminaryPage 18 of 583ppc440x5LOF.fm.September 12, 2002Figure A-2. B Instruction Format ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 180 of 589intrupts.fm.September 12, 2002Machine Check Save/Restore Register 1 (MCSRR1)Set to the conten

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 181 of 589See Machine Check Interrupts on page 161 for more information o

User’s ManualPPC440x5 CPU Core PreliminaryPage 182 of 589intrupts.fm.September 12, 2002instructions not with the execution of instructions. Data Stora

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 183 of 589• dcbtstFor all other instructions, if a Data Storage exception

User’s ManualPPC440x5 CPU Core PreliminaryPage 184 of 589intrupts.fm.September 12, 2002AP Set to 1 if the instruction causing the interrupt is an auxi

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 185 of 589Machine State Register (MSR)CE, ME, DE Unchanged.All other MSR

User’s ManualPPC440x5 CPU Core PreliminaryPage 186 of 589intrupts.fm.September 12, 2002• An integer load or store instruction that references a data s

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 187 of 589Exception Syndrome Register (ESR)FP Set to 1 if the instruction

User’s ManualPPC440x5 CPU Core PreliminaryPage 188 of 589intrupts.fm.September 12, 2002exception will cause a Debug interrupt to occur, rather than a

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 189 of 589was already being presented to the interrupt mechanism at the t

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5LOT.fm.September 12, 2002Page 19 of 583TablesTable 2-1. Data Operand Definitions ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 190 of 589intrupts.fm.September 12, 2002Programming Note: The ESR[PCRE,PCMP,PCRF] fields are provided to

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 191 of 589Save/Restore Register 1 (SRR1)Set to the contents of the MSR at

User’s ManualPPC440x5 CPU Core PreliminaryPage 192 of 589intrupts.fm.September 12, 2002Save/Restore Register 1 (SRR1)Set to the contents of the MSR at

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 193 of 589Critical Save/Restore Register 0 (CSRR0)Set to the effective ad

User’s ManualPPC440x5 CPU Core PreliminaryPage 194 of 589intrupts.fm.September 12, 2002Save/Restore Register 0 (SRR0)Set to the effective address of t

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 195 of 589When an Instruction TLB Error interrupt occurs, the processor s

User’s ManualPPC440x5 CPU Core PreliminaryPage 196 of 589intrupts.fm.September 12, 2002specified by the various debug facility registers. This excepti

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 197 of 589Programming Note: It is a programming error for software to ena

User’s ManualPPC440x5 CPU Core PreliminaryPage 198 of 589intrupts.fm.September 12, 2002Since the ICMP Debug exception does not suppress the execution

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 199 of 5896.6 Interrupt Ordering and MaskingIt is possible for multiple e

®Copyright and Disclaimer© Copyright International Business Machines Corporation 2002All Rights ReservedPrinted in the United States of America Septem

User’s ManualPPC440x5 CPU Core PreliminaryPage 20 of 583ppc440x5LOT.fm.September 12, 2002Table 5-4. Access Control Applied to Cache Management Instru

User’s ManualPPC440x5 CPU Core PreliminaryPage 200 of 589intrupts.fm.September 12, 2002This prevents any asynchronous interrupts, as well as (in the c

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 201 of 589interrupt may have occurred from within a non-critical class in

User’s ManualPPC440x5 CPU Core PreliminaryPage 202 of 589intrupts.fm.September 12, 20026.7 Exception PrioritiesPowerPC Book-E requires all synchronous

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 203 of 589Only applies to the defined 64-bit load, store, and cache manag

User’s ManualPPC440x5 CPU Core PreliminaryPage 204 of 589intrupts.fm.September 12, 20024. Program (Illegal Instruction exception)This exception will o

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 205 of 589This exception will occur if an attached floating-point unit re

User’s ManualPPC440x5 CPU Core PreliminaryPage 206 of 589intrupts.fm.September 12, 2002instructions that are implemented within the PPC440x5 core. Thi

User’s ManualPreliminary PPC440x5 CPU Coreintrupts.fm.September 12, 2002Page 207 of 5896.7.9 Exception Priorities for Branch InstructionsThe following

User’s ManualPPC440x5 CPU Core PreliminaryPage 208 of 589intrupts.fm.September 12, 20024. Program (Illegal Instruction exception)Applies to all reserv

User’s ManualPreliminary PPC440x5 CPU Coretimers.fm.September 12, 2002Page 209 of 5897. Timer FacilitiesThe PPC440x5 provides four timer facilities: a

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5LOT.fm.September 12, 2002Page 21 of 583Table 9-31. Extended Mnemonics for tw ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 210 of 589timers.fm.September 12, 2002Software access to TBU and TBL is non-privileged for read but pri

User’s ManualPreliminary PPC440x5 CPU Coretimers.fm.September 12, 2002Page 211 of 589lwz Ry, lowerli Rz, 0 # set GPR Rz to 0mtspr TBL,Rz # force TBL t

User’s ManualPPC440x5 CPU Core PreliminaryPage 212 of 589timers.fm.September 12, 2002Using mtspr to force the DEC to 0 does not cause a Decrementer ex

User’s ManualPreliminary PPC440x5 CPU Coretimers.fm.September 12, 2002Page 213 of 589When a Fixed Interval Timer exception occurs, the exception statu

User’s ManualPPC440x5 CPU Core PreliminaryPage 214 of 589timers.fm.September 12, 2002avoid another Watchdog Timer interrupt due to the same exception

User’s ManualPreliminary PPC440x5 CPU Coretimers.fm.September 12, 2002Page 215 of 589Figure 7-6 illustrates the sequence of Watchdog Timer events whic

User’s ManualPPC440x5 CPU Core PreliminaryPage 216 of 589timers.fm.September 12, 20027.6 Timer Status Register (TSR)The TSR is a privileged SPR that r

User’s ManualPreliminary PPC440x5 CPU Coretimers.fm.September 12, 2002Page 217 of 5897.7 Freezing the Timer FacilitiesThe debug mechanism provides a m

User’s ManualPPC440x5 CPU Core PreliminaryPage 218 of 589timers.fm.September 12, 2002

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 219 of 5898. Debug FacilitiesThe debug facilities of the PPC440x5 include su

User’s ManualPPC440x5 CPU Core PreliminaryPage 22 of 583ppc440x5LOT.fm.September 12, 2002

User’s ManualPPC440x5 CPU Core PreliminaryPage 220 of 589debug.fm.September 12, 2002page 159 for a description of the MSR and Debug interrupts). When

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 221 of 589Debug wait mode is enabled by setting both MSR[DWE] and the debug

User’s ManualPPC440x5 CPU Core PreliminaryPage 222 of 589debug.fm.September 12, 20028.3.1 Instruction Address Compare (IAC) Debug EventIAC debug event

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 223 of 589Note that the IAC range auto-toggle mechanism can “switch” the IAC

User’s ManualPPC440x5 CPU Core PreliminaryPage 224 of 589debug.fm.September 12, 2002matches the IAC conditions and is in virtual address space 1 (MSR[

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 225 of 589status fields is summarized in Table 8-2The affect of the auto-tog

User’s ManualPPC440x5 CPU Core PreliminaryPage 226 of 589debug.fm.September 12, 2002interrupt has occurred imprecisely. On the other hand, if the IAC

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 227 of 589DAC Mode FieldDBCR2[DAC12M] controls the comparison mode for the D

User’s ManualPPC440x5 CPU Core PreliminaryPage 228 of 589debug.fm.September 12, 2002When the data address falls outside the specified range, either on

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 229 of 5898.3.2.2 DAC Debug Event ProcessingThe behavior of the PPC440x5 upo

User’s ManualPreliminary PPC440x5 CPU Corepreface.fm.September 12, 2002Page 23 of 589About This BookThis user’s manual provides the architectural over

User’s ManualPPC440x5 CPU Core PreliminaryPage 230 of 589debug.fm.September 12, 2002counter will contain the address of that instruction, and that ins

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 231 of 589dcbst, dcbfThe dcbst and dcbf instructions are considered “loads”

User’s ManualPPC440x5 CPU Core PreliminaryPage 232 of 589debug.fm.September 12, 2002Event on page 226 describes the DAC conditions. In addition to the

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 233 of 589In this mode, at least one data byte lane that is enabled by a DVC

User’s ManualPPC440x5 CPU Core PreliminaryPage 234 of 589debug.fm.September 12, 2002lswx, stswxDVC debug events do not occur for lswx or stswx instruc

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 235 of 5898.3.6 Return (RET) Debug EventRET debug events occur when RET debu

User’s ManualPPC440x5 CPU Core PreliminaryPage 236 of 589debug.fm.September 12, 2002that there is a special case of MSR[DE] = 1 at the time of the exe

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 237 of 5898.3.9 Unconditional Debug Event (UDE)UDE debug events occur when a

User’s ManualPPC440x5 CPU Core PreliminaryPage 238 of 589debug.fm.September 12, 20028.4 Debug ResetSoftware can initiate an immediate reset operation

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 239 of 589changing any of the debug facility register fields related to the D

User’s ManualPPC440x5 CPU Core PreliminaryPage 24 of 589preface.fm.September 12, 2002Contents, on page v.Figures, on page xi.Tables, on page xiii.Inde

User’s ManualPPC440x5 CPU Core PreliminaryPage 240 of 589debug.fm.September 12, 20028.6.2 Debug Control Register 1 (DBCR1)DBCR1 is an SPR that is used

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 241 of 5892:3 IAC1ERIAC 1 Effective/Real00 Effective (MSR[IS] = don’t care)

User’s ManualPPC440x5 CPU Core PreliminaryPage 242 of 589debug.fm.September 12, 200231 IAC34ATIAC3/4 Auto-Toggle Enable0 Disable IAC 3/4 auto-toggle1

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 243 of 5898.6.3 Debug Control Register 2 (DBCR2)DBCR2 is an SPR that is used

User’s ManualPPC440x5 CPU Core PreliminaryPage 244 of 589debug.fm.September 12, 20028.6.4 Debug Status Register (DBSR)The DBSR contains status on debu

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 245 of 5898.6.5 Instruction Address Compare Registers (IAC1–IAC4)The four IA

User’s ManualPPC440x5 CPU Core PreliminaryPage 246 of 589debug.fm.September 12, 20028.6.6 Data Address Compare Registers (DAC1–DAC2)The two DAC regist

User’s ManualPreliminary PPC440x5 CPU Coredebug.fm.September 12, 2002Page 247 of 5898.6.8 Debug Data Register (DBDR)The DBDR can be used for communica

User’s ManualPPC440x5 CPU Core PreliminaryPage 248 of 589debug.fm.September 12, 2002

Preliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 249 of 5899. Instruction SetDescriptions of the PPC440x5 instructions f

User’s ManualPreliminary PPC440x5 CPU Corepreface.fm.September 12, 2002Page 25 of 589•nx means the replication of x, n times (that is, x concatenated

PPC440x5 CPU Core User’s Manual PreliminaryPage 250 of 589instrset.fm.September 12, 20029.1 Instruction Set PortabilityTo support embedded real-time a

Preliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 251 of 589These instruction fields contain values, such as opcodes, tha

PPC440x5 CPU Core User’s Manual PreliminaryPage 252 of 589instrset.fm.September 12, 2002EA Effective address; the 32-bit address, derived by applying

Preliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 253 of 5899.3.1 Operator PrecedenceTable 9-3 lists the pseudocode opera

PPC440x5 CPU Core User’s Manual PreliminaryPage 254 of 589instrset.fm.September 12, 2002Common examples of these kinds of register changes include the

addAddPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 255 of 589addAdd(RT) ← (RA) + (RB)The sum of the contents of regi

addcAdd CarryingPPC440x5 CPU Core User’s Manual PreliminaryPage 256 of 589instrset.fm.September 12, 2002addcAdd Carrying(RT) ← (RA) + (RB)if (RA) + (R

addeAdd ExtendedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 257 of 589addeAdd Extended(RT) ← (RA) + (RB) + XER[CA]i

addiAdd ImmediatePPC440x5 CPU Core User’s Manual PreliminaryPage 258 of 589instrset.fm.September 12, 2002addiAdd Immediate(RT) ← (RA|0) + EXTS(IM)If t

addicAdd Immediate CarryingPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 259 of 589addicAdd Immediate Carrying(RT) ←

User’s ManualPPC440x5 CPU Core PreliminaryPage 26 of 589preface.fm.September 12, 2002

addic.Add Immediate Carrying and RecordPPC440x5 CPU Core User’s Manual PreliminaryPage 260 of 589instrset.fm.September 12, 2002addic.Add Immediate Car

addisAdd Immediate ShiftedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 261 of 589addisAdd Immediate Shifted(RT) ← (R

addmeAdd to Minus One ExtendedPPC440x5 CPU Core User’s Manual PreliminaryPage 262 of 589instrset.fm.September 12, 2002addmeAdd to Minus One Extended(R

addzeAdd to Zero ExtendedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 263 of 589addzeAdd to Zero Extended(RT) ← (RA)

andANDPPC440x5 CPU Core User’s Manual PreliminaryPage 264 of 589instrset.fm.September 12, 2002andAND(RA) ← (RS) ∧ (RB)The contents of register RS are

andcAND with ComplementPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 265 of 589andcAND with Complement(RA) ← (RS) ∧¬(

andi.AND ImmediatePPC440x5 CPU Core User’s Manual PreliminaryPage 266 of 589instrset.fm.September 12, 2002andi.AND Immediate(RA) ← (RS) ∧ (160 || IM)T

andis.AND Immediate ShiftedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 267 of 589andis.AND Immediate Shifted(RA) ←

bBranchPPC440x5 CPU Core User’s Manual PreliminaryPage 268 of 589instrset.fm.September 12, 2002bBranchIf AA = 1 thenLI← target6:29NIA ← EXTS(LI ||20)e

bcBranch ConditionalPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 269 of 589bcBranch Conditionalif BO2= 0 thenCTR← CT

User’s ManualPreliminary PPC440x5 CPU Coreoverview.fm.September 12, 2002Page 27 of 5891. OverviewThe IBM™ PowerPC™ 440x5 32-bit embedded processor cor

bcBranch ConditionalPPC440x5 CPU Core User’s Manual PreliminaryPage 270 of 589instrset.fm.September 12, 2002Table 9-8. Extended Mnemonics for bc, bca,

bcBranch ConditionalPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 271 of 589bdzfcr_bit, targetDecrement CTRBranch if

bcBranch ConditionalPPC440x5 CPU Core User’s Manual PreliminaryPage 272 of 589instrset.fm.September 12, 2002bge[cr_field,] targetBranch if greater tha

bcBranch ConditionalPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 273 of 589bne[cr_field,] targetBranch if not equal.

bcBranch ConditionalPPC440x5 CPU Core User’s Manual PreliminaryPage 274 of 589instrset.fm.September 12, 2002bnu[cr_field,] targetBranch if not unorder

bcctrBranch Conditional to Count RegisterPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 275 of 589bcctrBranch Conditio

bcctrBranch Conditional to Count RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 276 of 589instrset.fm.September 12, 2002beqctr[cr_field]Branc

bcctrBranch Conditional to Count RegisterPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 277 of 589bngctr[cr_field]Bran

bclrBranch Conditional to Link RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 278 of 589instrset.fm.September 12, 2002bclrBranch Conditional

bclrBranch Conditional to Link RegisterPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 279 of 589Table 9-10. Extended M

User’s ManualPPC440x5 CPU Core PreliminaryPage 28 of 589overview.fm.September 12, 2002• 9-port (6-read, 3-write) 32x32-bit General Purpose Register (G

bclrBranch Conditional to Link RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 280 of 589instrset.fm.September 12, 2002beqlr[cr_field]Branch i

bclrBranch Conditional to Link RegisterPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 281 of 589bnglr[cr_field]Branch,

cmpComparePPC440x5 CPU Core User’s Manual PreliminaryPage 282 of 589instrset.fm.September 12, 2002cmpComparec0:3←40if (RA) < (RB) then c0← 1if (RA)

cmpiCompare ImmediatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 283 of 589cmpiCompare Immediatec0:3←40if (RA) <

cmplCompare LogicalPPC440x5 CPU Core User’s Manual PreliminaryPage 284 of 589instrset.fm.September 12, 2002cmplCompare Logicalc0:3←40if (RA) (RB) then

cmpliCompare Logical ImmediatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 285 of 589cmpliCompare Logical Immediatec

cntlzwCount Leading Zeros WordPPC440x5 CPU Core User’s Manual PreliminaryPage 286 of 589instrset.fm.September 12, 2002cntlzwCount Leading Zeros Wordn

crandCondition Register ANDPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 287 of 589crandCondition Register ANDCRBT← C

crandcCondition Register AND with ComplementPPC440x5 CPU Core User’s Manual PreliminaryPage 288 of 589instrset.fm.September 12, 2002crandcCondition Re

creqvCondition Register EquivalentPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 289 of 589creqvCondition Register Equ

User’s ManualPreliminary PPC440x5 CPU Coreoverview.fm.September 12, 2002Page 29 of 589– Decrementer with auto-reload capability– Fixed Interval Timer

crnandCondition Register NANDPPC440x5 CPU Core User’s Manual PreliminaryPage 290 of 589instrset.fm.September 12, 2002crnandCondition Register NANDCRBT

crnorCondition Register NORPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 291 of 589crnorCondition Register NORCRBT←¬(

crorCondition Register ORPPC440x5 CPU Core User’s Manual PreliminaryPage 292 of 589instrset.fm.September 12, 2002crorCondition Register ORCRBT← CRBA∨

crorcCondition Register OR with ComplementPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 293 of 589crorcCondition Regi

crxorCondition Register XORPPC440x5 CPU Core User’s Manual PreliminaryPage 294 of 589instrset.fm.September 12, 2002crxorCondition Register XORCRBT← CR

dcbaData Cache Block AllocatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 295 of 589dcba Data Cache Block Allocatedc

dcbfData Cache Block FlushPPC440x5 CPU Core User’s Manual PreliminaryPage 296 of 589instrset.fm.September 12, 2002dcbfData Cache Block FlushEA ← (RA|0

dcbiData Cache Block InvalidatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 297 of 589dcbiData Cache Block Invalidat

dcbstData Cache Block StorePPC440x5 CPU Core User’s Manual PreliminaryPage 298 of 589instrset.fm.September 12, 2002dcbstData Cache Block StoreEA ← (RA

dcbtData Cache Block TouchPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 299 of 589dcbtData Cache Block TouchEA ← (RA|

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5TOC.fm.September 12, 2002Page 3 of 583ContentsFigures ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 30 of 589overview.fm.September 12, 20021.3 PPC440x5 OrganizationThe PPC440x5 core includes a seven-stag

dcbtstData Cache Block Touch for StorePPC440x5 CPU Core User’s Manual PreliminaryPage 300 of 589instrset.fm.September 12, 2002dcbtst Data Cache Block

dcbtstData Cache Block Touch for StorePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 301 of 589This instruction is con

dcbzData Cache Block Set to ZeroPPC440x5 CPU Core User’s Manual PreliminaryPage 302 of 589instrset.fm.September 12, 2002dcbz Data Cache Block Set to Z

dcbzData Cache Block Set to ZeroPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 303 of 589This instruction is considere

dccciData Cache Congruence Class InvalidatePPC440x5 CPU Core User’s Manual PreliminaryPage 304 of 589instrset.fm.September 12, 2002dccci Data Cache Co

dcreadData Cache ReadPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 305 of 589dcreadData Cache ReadEA ← (RA|0) + (RB)I

dcreadData Cache ReadPPC440x5 CPU Core User’s Manual PreliminaryPage 306 of 589instrset.fm.September 12, 2002Registers Altered•RT• DCDBTRH• DCDBTRLInv

divwDivide WordPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 307 of 589divw Divide Word(RT) ← (RA) ÷ (RB)The contents

divwuDivide Word UnsignedPPC440x5 CPU Core User’s Manual PreliminaryPage 308 of 589instrset.fm.September 12, 2002divwuDivide Word Unsigned(RT) ← (RA)

dlmzbDetermine Leftmost Zero BytePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 309 of 589dlmzbdetermine left most zer

User’s ManualPreliminary PPC440x5 CPU Coreoverview.fm.September 12, 2002Page 31 of 5891.3.2 Execution PipelinesThe PPC440x5 core contains three execut

eqvEquivalentPPC440x5 CPU Core User’s Manual PreliminaryPage 310 of 589instrset.fm.September 12, 2002eqvEquivalent(RA) ←¬((RS) ⊕ (RB))The contents of

extsbExtend Sign BytePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 311 of 589extsbExtend Sign Byte(RA) ← EXTS(RS)24:3

extshExtend Sign HalfwordPPC440x5 CPU Core User’s Manual PreliminaryPage 312 of 589instrset.fm.September 12, 2002extshExtend Sign Halfword(RA) ← EXTS(

icbiInstruction Cache Block InvalidatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 313 of 589icbiInstruction Cache B

icbtInstruction Cache Block TouchPPC440x5 CPU Core User’s Manual PreliminaryPage 314 of 589instrset.fm.September 12, 2002icbtInstruction Cache Block T

icbtInstruction Cache Block TouchPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 315 of 589This instruction is consider

iccciInstruction Cache Congruence Class InvalidatePPC440x5 CPU Core User’s Manual PreliminaryPage 316 of 589instrset.fm.September 12, 2002iccciInstruc

icreadInstruction Cache ReadPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 317 of 589icreadInstruction Cache ReadEA ←

icreadInstruction Cache ReadPPC440x5 CPU Core User’s Manual PreliminaryPage 318 of 589instrset.fm.September 12, 2002Registers Altered• ICDBDR• ICDBTRH

iselInteger SelectPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 319 of 589iselAdd Immediateif CR[CRb] = 1 then(RT)← (

User’s ManualPPC440x5 CPU Core PreliminaryPage 32 of 589overview.fm.September 12, 2002The ICC supports cache line locking, at either an 8-line or 16-l

isyncInstruction SynchronizePPC440x5 CPU Core User’s Manual PreliminaryPage 320 of 589instrset.fm.September 12, 2002isyncInstruction SynchronizeThe is

lbzLoad Byte and ZeroPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 321 of 589lbzLoad Byte and ZeroEA ← (RA|0) + EXTS(

lbzuLoad Byte and Zero with UpdatePPC440x5 CPU Core User’s Manual PreliminaryPage 322 of 589instrset.fm.September 12, 2002lbzuLoad Byte and Zero with

lbzuxLoad Byte and Zero with Update IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 323 of 589lbzuxLoad Byte and

lbzxLoad Byte and Zero IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 324 of 589instrset.fm.September 12, 2002lbzxLoad Byte and Zero IndexedEA

lhaLoad Halfword AlgebraicPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 325 of 589lhaLoad Halfword AlgebraicEA ← (RA|

lhauLoad Halfword Algebraic with UpdatePPC440x5 CPU Core User’s Manual PreliminaryPage 326 of 589instrset.fm.September 12, 2002lhauLoad Halfword Algeb

lhauxLoad Halfword Algebraic with Update IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 327 of 589lhauxLoad Hal

lhaxLoad Halfword Algebraic IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 328 of 589instrset.fm.September 12, 2002lhaxLoad Halfword Algebraic

lhbrxLoad Halfword Byte-Reverse IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 329 of 589lhbrxLoad Halfword Byt

User’s ManualPreliminary PPC440x5 CPU Coreoverview.fm.September 12, 2002Page 33 of 589The translation lookaside buffer (TLB) is the primary hardware r

lhzLoad Halfword and ZeroPPC440x5 CPU Core User’s Manual PreliminaryPage 330 of 589instrset.fm.September 12, 2002lhzLoad Halfword and ZeroEA ← (RA|0)

lhzuLoad Halfword and Zero with UpdatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 331 of 589lhzuLoad Halfword and Z

lhzuxLoad Halfword and Zero with Update IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 332 of 589instrset.fm.September 12, 2002lhzuxLoad Halfw

lhzxLoad Halfword and Zero IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 333 of 589lhzxLoad Halfword and Zero

lmwLoad Multiple WordPPC440x5 CPU Core User’s Manual PreliminaryPage 334 of 589instrset.fm.September 12, 2002lmwLoad Multiple WordEA ← (RA|0) + EXTS(D

lswiLoad String Word ImmediatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 335 of 589lswiLoad String Word ImmediateE

lswiLoad String Word ImmediatePPC440x5 CPU Core User’s Manual PreliminaryPage 336 of 589instrset.fm.September 12, 2002• RA is in the range of register

lswxLoad String Word IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 337 of 589lswxLoad String Word IndexedEA ←

lswxLoad String Word IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 338 of 589instrset.fm.September 12, 2002Programming NoteThis instruction c

lwarxLoad Word and Reserve IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 339 of 589lwarxLoad Word and Reserve

User’s ManualPPC440x5 CPU Core PreliminaryPage 34 of 589overview.fm.September 12, 20021.3.5 TimersThe PPC440x5 contains a Time Base and three timers:

lwbrxLoad Word Byte-Reverse IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 340 of 589instrset.fm.September 12, 2002lwbrxLoad Word Byte-Reverse

lwzLoad Word and ZeroPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 341 of 589lwzLoad Word and ZeroEA ← (RA|0) + EXTS(

lwzuLoad Word and Zero with UpdatePPC440x5 CPU Core User’s Manual PreliminaryPage 342 of 589instrset.fm.September 12, 2002lwzuLoad Word and Zero with

lwzuxLoad Word and Zero with Update IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 343 of 589lwzuxLoad Word and

lwzxLoad Word and Zero IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 344 of 589instrset.fm.September 12, 2002lwzxLoad Word and Zero IndexedEA

macchwMultiply Accumulate Cross Halfword to Word Modulo SignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 345 of 58

macchwsMultiply Accumulate Cross Halfword to Word Saturate SignedPPC440x5 CPU Core User’s Manual PreliminaryPage 346 of 589instrset.fm.September 12, 2

macchwsuMultiply Accumulate Cross Halfword to Word Saturate UnsignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 347

macchwuMultiply Accumulate Cross Halfword to Word Modulo UnsignedPPC440x5 CPU Core User’s Manual PreliminaryPage 348 of 589instrset.fm.September 12, 2

machhwMultiply Accumulate High Halfword to Word Modulo SignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 349 of 589

User’s ManualPreliminary PPC440x5 CPU Coreoverview.fm.September 12, 2002Page 35 of 589tion in real time. Debug wait mode enables the processor to cont

machhwsMultiply Accumulate High Halfword to Word Saturate SignedPPC440x5 CPU Core User’s Manual PreliminaryPage 350 of 589instrset.fm.September 12, 20

machhwsuMultiply Accumulate High Halfword to Word Saturate UnsignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 351

machhwuMultiply Accumulate High Halfword to Word Modulo UnsignedPPC440x5 CPU Core User’s Manual PreliminaryPage 352 of 589instrset.fm.September 12, 20

maclhwMultiply Accumulate Low Halfword to Word Modulo SignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 353 of 589m

maclhwsMultiply Accumulate Low Halfword to Word Saturate SignedPPC440x5 CPU Core User’s Manual PreliminaryPage 354 of 589instrset.fm.September 12, 200

maclhwsuMultiply Accumulate Low Halfword to Word Saturate UnsignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 355 o

maclhwuMultiply Accumulate Low Halfword to Word Modulo UnsignedPPC440x5 CPU Core User’s Manual PreliminaryPage 356 of 589instrset.fm.September 12, 200

mbarMemory BarrierPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 357 of 589mbarMemory BarrierThe mbar instruction ensu

mcrfMove Condition Register FieldPPC440x5 CPU Core User’s Manual PreliminaryPage 358 of 589instrset.fm.September 12, 2002mcrfMove Condition Register F

mcrxrMove to Condition Register from XERPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 359 of 589mcrxrMove to Conditio

User’s ManualPPC440x5 CPU Core PreliminaryPage 36 of 589overview.fm.September 12, 20021.4.1 Processor Local Bus (PLB)There are three independent 128-b

mfcrMove From Condition RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 360 of 589instrset.fm.September 12, 2002mfcrMove From Condition Regist

mfdcrMove from Device Control RegisterPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 361 of 589mfdcrMove from Device C

mfmsrMove From Machine State RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 362 of 589instrset.fm.September 12, 2002mfmsrMove From Machine St

mfsprMove From Special Purpose RegisterPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 363 of 589mfsprMove From Special

mfsprMove From Special Purpose RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 364 of 589instrset.fm.September 12, 2002Table 9-19. Extended Mn

mfsprMove From Special Purpose RegisterPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 365 of 589mfivor5mfivor6mfivor7mfivo

msyncMemory SynchronizePPC440x5 CPU Core User’s Manual PreliminaryPage 366 of 589instrset.fm.September 12, 2002msyncMemory SynchronizeThe msync instru

mtcrfMove to Condition Register FieldsPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 367 of 589mtcrfMove to Condition

mtdcrMove To Device Control RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 368 of 589instrset.fm.September 12, 2002mtdcrMove To Device Contro

mtmsrMove To Machine State RegisterPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 369 of 589mtmsrMove To Machine State

User’s ManualPreliminary PPC440x5 CPU Coreoverview.fm.September 12, 2002Page 37 of 589PowerPC floating point unit (single or double precision), multim

mtsprMove To Special Purpose RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 370 of 589instrset.fm.September 12, 2002mtsprMove To Special Purp

mtsprMove To Special Purpose RegisterPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 371 of 589Table 9-22. Extended Mne

mtsprMove To Special Purpose RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 372 of 589instrset.fm.September 12, 2002mtivor5mtivor6mtivor7mtiv

mulchwMultiply Cross Halfword to Word SignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 373 of 589mulchwMultiply Cr

mulchwuMultiply Cross Halfword to Word UnsignedPPC440x5 CPU Core User’s Manual PreliminaryPage 374 of 589instrset.fm.September 12, 2002mulchwuMultiply

mulhhwMultiply High Halfword to Word SignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 375 of 589mulhhwMultiply Hig

mulhhwuMultiply High Halfword to Word UnsignedPPC440x5 CPU Core User’s Manual PreliminaryPage 376 of 589instrset.fm.September 12, 2002mulhhwuMultiply

mulhwMultiply High WordPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 377 of 589mulhwMultiply High Wordprod0:63← (RA)

mulhwuMultiply High Word UnsignedPPC440x5 CPU Core User’s Manual PreliminaryPage 378 of 589instrset.fm.September 12, 2002mulhwuMultiply High Word Unsi

mullhwMultiply Low Halfword to Word SignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 379 of 589mullhwMultiply High

User’s ManualPPC440x5 CPU Core PreliminaryPage 38 of 589overview.fm.September 12, 2002

mullhwuMultiply Low Halfword to Word UnsignedPPC440x5 CPU Core User’s Manual PreliminaryPage 380 of 589instrset.fm.September 12, 2002mullhwuMultiply H

mulliMultiply Low ImmediatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 381 of 589mulliMultiply Low Immediateprod0:4

mullwMultiply Low WordPPC440x5 CPU Core User’s Manual PreliminaryPage 382 of 589instrset.fm.September 12, 2002mullwMultiply Low Wordprod0:63← (RA) × (

nandNANDPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 383 of 589nandNAND(RA) ←¬((RS) ∧ (RB))The contents of register

negNegatePPC440x5 CPU Core User’s Manual PreliminaryPage 384 of 589instrset.fm.September 12, 2002negNegate(RT) ←¬(RA) + 1The twos complement of the co

nmacchwNegative Multiply Accumulate Cross Halfword to Word Modulo SignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page

nmacchwsNegative Multiply Accumulate Cross Halfword to Word Saturate SignedPPC440x5 CPU Core User’s Manual PreliminaryPage 386 of 589instrset.fm.Septe

nmachhwNegative Multiply Accumulate High Halfword to Word Modulo SignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page

nmachhwsNegative Multiply Accumulate High Halfword to Word Saturate SignedPPC440x5 CPU Core User’s Manual PreliminaryPage 388 of 589instrset.fm.Septem

nmaclhwNegative Multiply Accumulate Low Halfword to Word Modulo SignedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 3

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 39 of 5892. Programming ModelThe programming model of the PPC440x5 core d

nmaclhwsNegative Multiply Accumulate High Halfword to Word Saturate SignedPPC440x5 CPU Core User’s Manual PreliminaryPage 390 of 589instrset.fm.Septem

norNORPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 391 of 589norNOR(RA) ←¬((RS) ∨ (RB))The contents of register RS i

orORPPC440x5 CPU Core User’s Manual PreliminaryPage 392 of 589instrset.fm.September 12, 2002orOR(RA) ← (RS) ∨ (RB)The contents of register RS is ORed

orcOR with ComplementPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 393 of 589orcOR with Complement(RA) ← (RS) ∨¬(RB)T

oriOR ImmediatePPC440x5 CPU Core User’s Manual PreliminaryPage 394 of 589instrset.fm.September 12, 2002oriOR Immediate(RA) ← (RS) ∨ (160 || IM)The IM

orisOR Immediate ShiftedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 395 of 589orisOR Immediate Shifted(RA) ← (RS) ∨

rfciReturn From Critical InterruptPPC440x5 CPU Core User’s Manual PreliminaryPage 396 of 589instrset.fm.September 12, 2002rfciReturn From Critical Int

rfiReturn From InterruptPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 397 of 589rfiReturn From Interrupt(PC) ← (SRR0)(

rfmciReturn From Machine Check InterruptPPC440x5 CPU Core User’s Manual PreliminaryPage 398 of 589instrset.fm.September 12, 2002rfmciReturn From Criti

rlwimiRotate Left Word Immediate then Mask InsertPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 399 of 589rlwimiRotate

User’s ManualPPC440x5 CPU Core PreliminaryPage 4 of 583ppc440x5TOC.fm.September 12, 20022.3.2 Allocated Instruction Class ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 40 of 589prgmodel.fm.September 12, 2002Data storage operands for storage access instructions have the f

rlwinmRotate Left Word Immediate then AND with MaskPPC440x5 CPU Core User’s Manual PreliminaryPage 400 of 589instrset.fm.September 12, 2002rlwinmRotat

rlwinmRotate Left Word Immediate then AND with MaskPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 401 of 589clrrwiRA,

rlwinmRotate Left Word Immediate then AND with MaskPPC440x5 CPU Core User’s Manual PreliminaryPage 402 of 589instrset.fm.September 12, 2002srwiRA, RS,

rlwnmRotate Left Word then AND with MaskPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 403 of 589rlwnmRotate Left Word

scSystem CallPPC440x5 CPU Core User’s Manual PreliminaryPage 404 of 589instrset.fm.September 12, 2002scSystem CallSRR1 ← MSRSRR0 ← 4 + address of sc i

slwShift Left WordPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 405 of 589slwShift Left Wordn ← (RB)26:31r ← ROTL((RS

srawShift Right Algebraic WordPPC440x5 CPU Core User’s Manual PreliminaryPage 406 of 589instrset.fm.September 12, 2002srawShift Right Algebraic Wordn

srawiShift Right Algebraic Word ImmediatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 407 of 589srawiShift Right Alg

srwShift Right WordPPC440x5 CPU Core User’s Manual PreliminaryPage 408 of 589instrset.fm.September 12, 2002srwShift Right Wordn ← (RB)26:31r ← ROTL((R

stbStore BytePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 409 of 589stbStore ByteEA ← (RA|0) + EXTS(D)MS(EA, 1)← (RS

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 41 of 589Similarly, the TLB management instructions access page operands,

stbuStore Byte with UpdatePPC440x5 CPU Core User’s Manual PreliminaryPage 410 of 589instrset.fm.September 12, 2002stbuStore Byte with UpdateEA ← (RA|0

stbuxStore Byte with Update IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 411 of 589stbuxStore Byte with Updat

stbxStore Byte IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 412 of 589instrset.fm.September 12, 2002stbxStore Byte IndexedEA ← (RA|0) + (RB)

sthStore HalfwordPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 413 of 589sthStore HalfwordEA ← (RA|0) + EXTS(D)MS(EA,

sthbrxStore Halfword Byte-Reverse IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 414 of 589instrset.fm.September 12, 2002sthbrxStore Halfword

sthuStore Halfword with UpdatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 415 of 589sthuStore Halfword with UpdateE

sthuxStore Halfword with Update IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 416 of 589instrset.fm.September 12, 2002sthuxStore Halfword wit

sthxStore Halfword IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 417 of 589sthxStore Halfword IndexedEA ← (RA|

stmwStore Multiple WordPPC440x5 CPU Core User’s Manual PreliminaryPage 418 of 589instrset.fm.September 12, 2002stmwStore Multiple WordEA ← (RA|0) + EX

stswiStore String Word ImmediatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 419 of 589stswiStore String Word Immedi

User’s ManualPPC440x5 CPU Core PreliminaryPage 42 of 589prgmodel.fm.September 12, 2002The 14-bit BD field is concatenated on the right with 0b00, sign

stswiStore String Word ImmediatePPC440x5 CPU Core User’s Manual PreliminaryPage 420 of 589instrset.fm.September 12, 2002Programming NoteThis instructi

stswxStore String Word IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 421 of 589stswxStore String Word IndexedE

stwStore WordPPC440x5 CPU Core User’s Manual PreliminaryPage 422 of 589instrset.fm.September 12, 2002stwStore WordEA ← (RA|0) + EXTS(D)MS(EA, 4)← (RS)

stwbrxStore Word Byte-Reverse IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 423 of 589stwbrxStore Word Byte-Re

stwcx.Store Word Conditional IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 424 of 589instrset.fm.September 12, 2002stwcx.Store Word Condition

stwcx.Store Word Conditional IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 425 of 589The PowerPC Book-E archit

stwuStore Word with UpdatePPC440x5 CPU Core User’s Manual PreliminaryPage 426 of 589instrset.fm.September 12, 2002stwuStore Word with UpdateEA ← (RA|0

stwuxStore Word with Update IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 427 of 589stwuxStore Word with Updat

stwxStore Word IndexedPPC440x5 CPU Core User’s Manual PreliminaryPage 428 of 589instrset.fm.September 12, 2002stwxStore Word IndexedEA ← (RA|0) + (RB)

subfSubtract FromPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 429 of 589subfSubtract From(RT) ←¬(RA) + (RB) + 1The s

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 43 of 589• The ordering that assigns the lowest address to the highest-or

subfcSubtract From CarryingPPC440x5 CPU Core User’s Manual PreliminaryPage 430 of 589instrset.fm.September 12, 2002subfcSubtract From Carrying(RT) ←¬(

subfeSubtract From ExtendedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 431 of 589subfeSubtract From Extended(RT) ←¬

subficSubtract From Immediate CarryingPPC440x5 CPU Core User’s Manual PreliminaryPage 432 of 589instrset.fm.September 12, 2002subficSubtract From Immed

subfmeSubtract from Minus One ExtendedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 433 of 589subfmeSubtract from Min

subfzeSubtract from Zero ExtendedPPC440x5 CPU Core User’s Manual PreliminaryPage 434 of 589instrset.fm.September 12, 2002subfzeSubtract from Zero Exte

tlbreTLB Read EntryPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 435 of 589tlbreTLB Read Entrytlbentry ← TLB[(RA)26:3

tlbreTLB Read EntryPPC440x5 CPU Core User’s Manual PreliminaryPage 436 of 589instrset.fm.September 12, 2002Registers Altered•RT• MMUCR[STID] (if WS =

tlbsxTLB Search IndexedPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 437 of 589tlbsxTLB Search IndexedEA ← (RA|0) + (

tlbsyncTLB SynchronizePPC440x5 CPU Core User’s Manual PreliminaryPage 438 of 589instrset.fm.September 12, 2002tlbsyncTLB SynchronizeThe tlbsync instru

tlbweTLB Write EntryPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 439 of 589tlbweTLB Write Entrytlbentry ← TLB[(RA)26

User’s ManualPPC440x5 CPU Core PreliminaryPage 44 of 589prgmodel.fm.September 12, 2002Big Endian MappingThe big endian mapping of structure s follows

twTrap WordPPC440x5 CPU Core User’s Manual PreliminaryPage 440 of 589instrset.fm.September 12, 2002twTrap Wordif ( ((RA) (RB) ∧ TO0=1) ∨((RA) (RB) ∧ T

twTrap WordPreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 441 of 589The enabling of trap debug events may affect the i

twTrap WordPPC440x5 CPU Core User’s Manual PreliminaryPage 442 of 589instrset.fm.September 12, 2002twngRA, RBTrap if (RA) not greater than (RB).Extend

twiTrap Word ImmediatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 443 of 589twiTrap Word Immediateif ( ((RA) EXTS(I

twiTrap Word ImmediatePPC440x5 CPU Core User’s Manual PreliminaryPage 444 of 589instrset.fm.September 12, 2002The enabling of trap debug events may af

twiTrap Word ImmediatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 445 of 589twnliRA, IMTrap if (RA) not less than E

wrteeWrite External EnablePPC440x5 CPU Core User’s Manual PreliminaryPage 446 of 589instrset.fm.September 12, 2002wrteeWrite External EnableMSR[EE] ←

wrteeiWrite External Enable ImmediatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 447 of 589wrteeiWrite External Ena

xorXORPPC440x5 CPU Core User’s Manual PreliminaryPage 448 of 589instrset.fm.September 12, 2002xorXOR(RA) ← (RS) ⊕ (RB)The contents of register RS are

xoriXOR ImmediatePreliminary PPC440x5 CPU Core User’s Manualinstrset.fm.September 12, 2002 Page 449 of 589xoriXOR Immediate(RA) ← (RS) ⊕ (160 || IM)Th

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 45 of 589On the other hand, in a little endian mapping the same instructi

xorisXOR Immediate ShiftedPPC440x5 CPU Core User’s Manual PreliminaryPage 450 of 589instrset.fm.September 12, 2002xorisXOR Immediate Shifted(RA) ← (RS

User’s ManualPreliminary PPC440x5 CPU CoreregsummIntro.fm.September 12, 2002Page 451 of 58910. Register SummaryThis chapter provides an alphabetical

User’s ManualPPC440x5 CPU Core PreliminaryPage 452 of 589regsummIntro.fm.September 12, 2002Table 10-1. Register CategoriesRegister Category Register(s

User’s ManualPreliminary PPC440x5 CPU CoreregsummIntro.fm.September 12, 2002Page 453 of 589TimerDEC Supervisor SPR 211DECAR Supervisor, write-only SPR

User’s ManualPPC440x5 CPU Core PreliminaryPage 454 of 589regsummIntro.fm.September 12, 2002Table 10-2 Special Purpose Registers Sorted by SPR Number o

User’s ManualPreliminary PPC440x5 CPU CoreregsummIntro.fm.September 12, 2002Page 455 of 589SPRG3 Special Purpose Register General 3 0x113 Supervisor R

User’s ManualPPC440x5 CPU Core PreliminaryPage 456 of 589regsummIntro.fm.September 12, 2002IVOR14 Interrupt Vector Offset Register 14 0x19E Supervisor

User’s ManualPreliminary PPC440x5 CPU CoreregsummIntro.fm.September 12, 2002Page 457 of 58910.2 Reserved FieldsFor all registers with fields marked as

User’s ManualPPC440x5 CPU Core PreliminaryPage 458 of 589regsummIntro.fm.September 12, 2002

Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 459 of 5890.Register Summary10.4 Alphabetical Register ListingThe

User’s ManualPPC440x5 CPU Core PreliminaryPage 46 of 589prgmodel.fm.September 12, 2002• For word loads and stores (including load/store multiple), byt

CCR0Core Configuration Register 0PPC440x5 CPU Core User’s Manual PreliminaryPage 460 of 589regsumm440core.fm.September 12, 2002CCR0SPR 0x3B3 Superviso

CCR0 (cont.)Core Configuration Register 0Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 461 of 58923 FLSTAForce

CCR1Core Configuration Register 1PPC440x5 CPU Core User’s Manual PreliminaryPage 462 of 589regsumm440core.fm.September 12, 2002CCR1SPR 0x378 Superviso

CCR1 (cont.)Core Configuration Register 1Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 463 of 58924 TCSTimer Cl

CRCondition RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 464 of 589regsumm440core.fm.September 12, 2002CRUser Read/WriteSee Condition Regis

CSRR0Critical Save/Restore Register 0Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 465 of 589CSRR0SPR 0x03A Sup

CSRR1Critical Save/Restore Register 1PPC440x5 CPU Core User’s Manual PreliminaryPage 466 of 589regsumm440core.fm.September 12, 2002CSRR1SPR 0x03B Supe

CTRCount RegisterPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 467 of 589CTRSPR 0x009 User R/WSee Count Registe

DAC1–DAC2Data Address Compare RegistersPPC440x5 CPU Core User’s Manual PreliminaryPage 468 of 589regsumm440core.fm.September 12, 2002DAC1–DAC2SPR 0x13

DBCR0Debug Control Register 0Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 469 of 589DBCR0SPR 0x134 Supervisor

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 47 of 5892.2 RegistersThis section provides an overview of the register c

DBCR0 (cont.)Debug Control Register 0PPC440x5 CPU Core User’s Manual PreliminaryPage 470 of 589regsumm440core.fm.September 12, 200212 DAC1RData Addres

DBCR1Debug Control Register 1Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 471 of 589DBCR1SPR 0x135 Supervisor

DBCR1 (cont.)Debug Control Register 1PPC440x5 CPU Core User’s Manual PreliminaryPage 472 of 589regsumm440core.fm.September 12, 200220:21 IAC4USIAC 4 U

DBCR2Debug Control Register 2Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 473 of 589DBCR2SPR 0x136 Supervisor

DBCR2 (cont.)Debug Control Register 2PPC440x5 CPU Core User’s Manual PreliminaryPage 474 of 589regsumm440core.fm.September 12, 200214:15 DVC2MDVC 2 Mo

DBDRDebug Data RegisterPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 475 of 589DBDRSPR 0x3F3 Supervisor R/WSee

DBSRDebug Status RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 476 of 589regsumm440core.fm.September 12, 2002DBSRSPR 0x130 Supervisor Read/C

DBSR (cont.)Debug Status RegisterPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 477 of 58913 DAC1WDAC 1 Write De

DCDBTRHData Cache Debug Tag Register HighPPC440x5 CPU Core User’s Manual PreliminaryPage 478 of 589regsumm440core.fm.September 12, 2002DCDBTRHSPR 0x39

DCDBTRLData Cache Debug Tag Register LowPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 479 of 589DCDBTRLSPR 0x39

User’s ManualPPC440x5 CPU Core PreliminaryPage 48 of 589prgmodel.fm.September 12, 2002Integer ProcessingGPR0GPR1GPR31GPR2•••Condition RegisterCRXERLin

DEARData Exception Address RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 480 of 589regsumm440core.fm.September 12, 2002DEARSPR 0x03D Supervi

DECDecrementerPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 481 of 589DECSPR 0x016 Supervisor R/WSee Decremente

DECARDecrementer Auto-ReloadPPC440x5 CPU Core User’s Manual PreliminaryPage 482 of 589regsumm440core.fm.September 12, 2002DECARSPR 0x036 Supervisor Wr

DNV0–DNV3Data Cache Normal Victim 0–3Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 483 of 589DNV0–DNV3SPR 0x390

DTV0–DTV3Data Cache Transient Victim 0–3PPC440x5 CPU Core User’s Manual PreliminaryPage 484 of 589regsumm440core.fm.September 12, 2002DTV0–DTV3SPR 0x3

DVC1–DVC2Data Value Compare RegistersPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 485 of 589DVC1–DVC2SPR 0x13E

DVLIMData Cache Victim LimitPPC440x5 CPU Core User’s Manual PreliminaryPage 486 of 589regsumm440core.fm.September 12, 2002DVLIMSPR 0x398 Supervisor R/

ESRException Syndrome RegisterPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 487 of 589ESRSPR 0x03E Supervisor R

ESR (cont.)Exception Syndrome RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 488 of 589regsumm440core.fm.September 12, 200214 BOByte Ordering

GPRGeneral Purpose RegistersPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 489 of 589GPR0–GPR31User R/WSee Gener

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 49 of 589Core Configuration RegistersCCR0CCR1PVRProcessor Version Register

IAC1–IAC4Instruction Address Compare RegistersPPC440x5 CPU Core User’s Manual PreliminaryPage 490 of 589regsumm440core.fm.September 12, 2002IAC1–IAC4S

ICDBDRInstruction Cache Debug Data RegisterPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 491 of 589ICDBDRSPR 0x

ICDBTRHInstruction Cache Debug Tag Register HighPPC440x5 CPU Core User’s Manual PreliminaryPage 492 of 589regsumm440core.fm.September 12, 2002ICDBTRHS

ICDBTRLInstruction Cache Debug Tag Register LowPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 493 of 589ICDBTRLS

INV0–INV3Instruction Cache Normal Victim 0–3PPC440x5 CPU Core User’s Manual PreliminaryPage 494 of 589regsumm440core.fm.September 12, 2002INV0–INV3SPR

ITV0–ITV3Instruction Cache Transient Victim 0–3Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 495 of 589ITV0–ITV

IVLIMInstruction Cache Victim LimitPPC440x5 CPU Core User’s Manual PreliminaryPage 496 of 589regsumm440core.fm.September 12, 2002IVLIMSPR 0x399 Superv

IVOR0–IVOR15Interrupt Vector Offset RegistersPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 497 of 589IVOR0–IVOR

IVPRInterrupt Vector Prefix RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 498 of 589regsumm440core.fm.September 12, 2002IVPRSPR 0x03F Superv

LRLink RegisterPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 499 of 589LRSPR 0x008 User R/WSee Link Register (L

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5TOC.fm.September 12, 2002Page 5 of 5832.10 Synchronization ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 50 of 589prgmodel.fm.September 12, 2002Table 2-3. Register CategoriesRegister Category Register(s) Mode

MCSRMachine Check Status RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 500 of 589regsumm440core.fm.September 12, 2002MCSRSPR 0x23C Superviso

MCSRR0Machine Check Save/Restore Register 0Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 501 of 589MCSRR0SPR 0x

MCSRR1Machine Check Save/Restore Register 1PPC440x5 CPU Core User’s Manual PreliminaryPage 502 of 589regsumm440core.fm.September 12, 2002MCSRR1SPR 0x2

MMUCRMemory Management Control RegisterPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 503 of 589MMUCRSPR 0x3B2 S

MSRMachine State RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 504 of 589regsumm440core.fm.September 12, 2002MSRSupervisor R/WSee Machine St

MSR (cont.)Machine State RegisterPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 505 of 58923 FE1Floating-point e

PIDProcess IDPPC440x5 CPU Core User’s Manual PreliminaryPage 506 of 589regsumm440core.fm.September 12, 2002PIDSPR 0x030 Supervisor R/WSee Process ID (

PIRProcessor Identification RegisterPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 507 of 589PIRSPR 0x11E Superv

PVRProcessor Version RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 508 of 589regsumm440core.fm.September 12, 2002PVRSPR 0x11F Supervisor Rea

RSTCFGReset ConfigurationPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 509 of 589RSTCFGSPR 39B Supervisor Read-

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 51 of 589TimerDEC Supervisor SPR 211DECAR Supervisor, write-only SPR 211T

SPRG0–SPRG7Special Purpose Register GeneralPPC440x5 CPU Core User’s Manual PreliminaryPage 510 of 589regsumm440core.fm.September 12, 2002SPRG0–SPRG7SP

SRR0Save/Restore Register 0Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 511 of 589SRR0SPR 0x01A Supervisor R/W

SRR1Save/Restore Register 1PPC440x5 CPU Core User’s Manual PreliminaryPage 512 of 589regsumm440core.fm.September 12, 2002SRR1SPR 0x01B Supervisor R/WS

TBLTime Base LowerPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 513 of 589TBLSPR 0x10C (User/Supervisor Read-On

TBUTime Base UpperPPC440x5 CPU Core User’s Manual PreliminaryPage 514 of 589regsumm440core.fm.September 12, 2002TBUSPR 0x10D (User/Supervisor Read-Onl

TCRTimer Control RegisterPreliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 515 of 589TCRSPR 0x154 Supervisor R/WSee

TSRTimer Status RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 516 of 589regsumm440core.fm.September 12, 2002TSRSPR 0x150 Supervisor Read/Cle

USPRG0User Special Purpose Register General 0Preliminary PPC440x5 CPU Core User’s Manualregsumm440core.fm.September 12, 2002 Page 517 of 589USPRG0SPR

XERInteger Exception RegisterPPC440x5 CPU Core User’s Manual PreliminaryPage 518 of 589regsumm440core.fm.September 12, 2002XERSPR 0x001 User R/WSee In

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 519 of 589Appendix A. Instruction SummaryThis appendix describes the vari

User’s ManualPPC440x5 CPU Core PreliminaryPage 52 of 589prgmodel.fm.September 12, 20022.2.1 Register TypesThere are five register types contained with

User’s ManualPPC440x5 CPU Core PreliminaryPage 520 of 589instalfa.fm.September 12, 2002A.1.1 Instruction FieldsPPC440x5 instructions contain various c

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 521 of 589Used in rotate-and-mask instructions to specify the ending bit

User’s ManualPPC440x5 CPU Core PreliminaryPage 522 of 589instalfa.fm.September 12, 2002A.1.2.1 I-FormA.1.2.2 B-FormA.1.2.3 SC-FormA.1.2.4 D-FormOPCD L

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 523 of 589A.1.2.5 X-FormOPCD RT RA RB XO RcOPCD RT RA RB XO /OPCD RT RA N

User’s ManualPPC440x5 CPU Core PreliminaryPage 524 of 589instalfa.fm.September 12, 2002A.1.2.6 XL-FormA.1.2.7 XFX-FormA.1.2.8 XO-FormA.1.2.9 M-FormA.2

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 525 of 589Table A-1 summarizes the PPC440x5 instruction set, including re

User’s ManualPPC440x5 CPU Core PreliminaryPage 526 of 589instalfa.fm.September 12, 2002addisRT, RA, IMAdd (IM ||160) to (RA|0).Place result in RT.261a

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 527 of 589bclrBO, BIBranch conditional to address in LR.Using (LR) at ent

User’s ManualPPC440x5 CPU Core PreliminaryPage 528 of 589instalfa.fm.September 12, 2002bdnztcr_bit, targetDecrement CTR.Branch if CTR ≠ 0 AND CRcr_bit

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 529 of 589bdztcr_bit, targetDecrement CTR.Branch if CTR = 0 AND CRcr_bit=

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 53 of 5892.2.1.4 Machine State RegisterThe Machine State Register (MSR) i

User’s ManualPPC440x5 CPU Core PreliminaryPage 530 of 589instalfa.fm.September 12, 2002bfctrcr_bitBranch if CRcr_bit= 0 to address in CTR.Extended mne

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 531 of 589bgtlr[cr_field]Branch if greater than to address in LR.Use CR[C

User’s ManualPPC440x5 CPU Core PreliminaryPage 532 of 589instalfa.fm.September 12, 2002bltctr[cr_field]Branch if less than to address in CTR.Use CR[CR

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 533 of 589bngctr[cr_field]Branch if not greater than to address in CTR.Us

User’s ManualPPC440x5 CPU Core PreliminaryPage 534 of 589instalfa.fm.September 12, 2002bnsctr[cr_field]Branch if not summary overflow to address in CT

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 535 of 589bsoctr[cr_field]Branch if summary overflow to address in CTR.Us

User’s ManualPPC440x5 CPU Core PreliminaryPage 536 of 589instalfa.fm.September 12, 2002bunlr[cr_field]Branch if unordered,to address in LR.Use CR[CR0]

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 537 of 589cmpwi[BF,] RA, IMCompare Word Immediate.UseCR[CR0] if BF is omi

User’s ManualPPC440x5 CPU Core PreliminaryPage 538 of 589instalfa.fm.September 12, 2002dcreadRT, RA, RBRead tag and data information from the data cac

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 539 of 589extsbRA, RSExtend the sign of byte (RS)24:31.Place the result i

User’s ManualPPC440x5 CPU Core PreliminaryPage 54 of 589prgmodel.fm.September 12, 2002• cause a Floating-Point Unavailable interrupt if the instructio

User’s ManualPPC440x5 CPU Core PreliminaryPage 540 of 589instalfa.fm.September 12, 2002lhauRT, D(RA)Load halfword from EA = (RA|0) + EXTS(D) and sign

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 541 of 589lswxRT, RA, RBLoad consecutive bytes from EA=(RA|0)+(RB).Number

User’s ManualPPC440x5 CPU Core PreliminaryPage 542 of 589instalfa.fm.September 12, 2002machhwRT, RA, RBprod0:31← (RA)16:31× (RB)0:15temp0:32← prod0:31

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 543 of 589mfcrRTMove from CR to RT,(RT) ← (CR).360mfdcrRT, DCRNMove from

User’s ManualPPC440x5 CPU Core PreliminaryPage 544 of 589instalfa.fm.September 12, 2002mfccr0mfccr1mfctrmfdac1mfdac2mfdbcr0mfdbcr1mfdbsrmfdccrmfdcwrmf

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 545 of 589mrRT, RSMove register.(RT) ← (RS)Extended mnemonic foror RT,RS,

User’s ManualPPC440x5 CPU Core PreliminaryPage 546 of 589instalfa.fm.September 12, 2002mtccr0mtccr1mtctrmtdac1mtdac2mtdbcr0mtdbcr1mtdbsrmtdccrmtdcwrmt

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 547 of 589mtsprSPRN, RSMove to SPR from RS,(SPR(SPRN)) ← (RS).370mulchwRT

User’s ManualPPC440x5 CPU Core PreliminaryPage 548 of 589instalfa.fm.September 12, 2002nmacchwsRT, RA, RBprod0:31← (RA)16:31× (RB)0:15temp0:32← –prod0

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 549 of 589rfiReturn from interrupt.(PC) ← (SRR0).(MSR) ← (SRR1).397rfmciRe

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 55 of 589In addition to supporting the defined instructions of PowerPC Bo

User’s ManualPPC440x5 CPU Core PreliminaryPage 550 of 589instalfa.fm.September 12, 2002slwiRA, RS, nShift left immediate. (n < 32)(RA)0:31-n← (RS)n

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 551 of 589sthuRS, D(RA)Store halfword (RS)16:31 in memory atEA = (RA|0) +

User’s ManualPPC440x5 CPU Core PreliminaryPage 552 of 589instalfa.fm.September 12, 2002subRT, RA, RBSubtract (RB) from (RA).(RT) ←¬(RB) + (RA) + 1.Ext

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 553 of 589subfzeRT, RA, RBSubtract (RA) from zero with carry-in.(RT) ←¬(R

User’s ManualPPC440x5 CPU Core PreliminaryPage 554 of 589instalfa.fm.September 12, 2002tlbsynctlbsync does not complete until all previous TLB-update

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 555 of 589trapTrap unconditionally.Extended mnemonic fortw 31,0,0440tweqR

User’s ManualPPC440x5 CPU Core PreliminaryPage 556 of 589instalfa.fm.September 12, 2002tweqiRA, IMTrap if (RA) equal to EXTS(IM).Extended mnemonic for

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 557 of 589A.3 Allocated Instruction OpcodesAllocated instructions are pro

User’s ManualPPC440x5 CPU Core PreliminaryPage 558 of 589instalfa.fm.September 12, 2002Table A-3 lists the reserved opcodes designated by PowerPC Book

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 559 of 589A.6 Implemented Instructions Sorted by OpcodeTable A-5 on page

User’s ManualPPC440x5 CPU Core PreliminaryPage 56 of 589prgmodel.fm.September 12, 20022.3.4 Reserved Instruction ClassThis class of instructions consi

User’s ManualPPC440x5 CPU Core PreliminaryPage 560 of 589instalfa.fm.September 12, 2002440 XmulhhwRT, RA, RB 375mulhhw.4 44 (556) XOmachhwRT, RA, RB 3

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 561 of 5894 236 (748) XOmacchwsRT, RA, RB 346macchws.macchwsomacchwso.4 2

User’s ManualPPC440x5 CPU Core PreliminaryPage 562 of 589instalfa.fm.September 12, 200216 BbcBO, BI, target 269bcabclbcla17 SCsc40418 Ibtarget 268babl

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 563 of 58931 8 (520) XOsubfcRT, RA, RB 430subfc.subfcosubfco.31 10 (522)

User’s ManualPPC440x5 CPU Core PreliminaryPage 564 of 589instalfa.fm.September 12, 200231 104 (616) XOnegRT, RA 384neg.negonego.31 119 XlbzuxRT, RA, R

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 565 of 58931 235 (747) XOmullwRT, RA, RB 382mullw.mullwomullwo.31 246 Xdc

User’s ManualPPC440x5 CPU Core PreliminaryPage 566 of 589instalfa.fm.September 12, 200231 491 (1003) XOdivwRT, RA, RB 307divw.divwodivwo.31 512 Xmcrxr

User’s ManualPreliminary PPC440x5 CPU Coreinstalfa.fm.September 12, 2002Page 567 of 58931 998 XicreadRA, RB 31731 1014 XdcbzRA, RB 30232 DlwzRT, D(RA)

User’s ManualPPC440x5 CPU Core PreliminaryPage 568 of 589instalfa.fm.September 12, 2002

User’s ManualPreliminary PPC440x5 CPU Coreoptimize.fm.September 12, 2002Page 569 of 589Appendix B. PPC440x5 Core Compiler OptimizationsThis appendix d

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 57 of 589Table 2-4 summarizes the PPC440x5 instruction set by category. I

User’s ManualPPC440x5 CPU Core PreliminaryPage 570 of 589optimize.fm.September 12, 2002If the CR-update is MAC or a 16 × 32 multiply, 1 to 3 instructi

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5IX.fm.September 12, 2002Page 571 of 583IndexAadd, 255add., 255addc, 256addc., 256addco, 256addco., 2

User’s ManualPPC440x5 CPU Core PreliminaryPage 572 of 583ppc440x5IX.fm.September 12, 2002bf, 271bfa, 271bfctr, 276bfctrl, 276bfl, 271bfla, 271bflr, 28

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5IX.fm.September 12, 2002Page 573 of 583btctrl, 277btl, 274btla, 274btlr, 281btlrl, 281bun, 274buna,

User’s ManualPPC440x5 CPU Core PreliminaryPage 574 of 583ppc440x5IX.fm.September 12, 2002data addressing modes, 41data cachecoherency, 124data cache a

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5IX.fm.September 12, 2002Page 575 of 583divwuo, 308divwuo., 308dlmzb, 309dlmzb., 309DNV0–DNV3, 483DTV

User’s ManualPPC440x5 CPU Core PreliminaryPage 576 of 583ppc440x5IX.fm.September 12, 2002bfl, 271bfla, 271bflr, 280bflrl, 280bge, 272bgea, 272bgectr,

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5IX.fm.September 12, 2002Page 577 of 583crclr, 294crmove, 292crnot, 291crset, 289extlwi, 401extlwi.,

User’s ManualPPC440x5 CPU Core PreliminaryPage 578 of 583ppc440x5IX.fm.September 12, 2002DCC, 115ICC, 103FIT, 212fixed interval timer, 212fixed interv

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5IX.fm.September 12, 2002Page 579 of 583crandc, 288creqv, 289crnand, 290crnor, 291cror, 292crorc, 293

User’s ManualPPC440x5 CPU Core PreliminaryPage 58 of 589prgmodel.fm.September 12, 2002an “indexed” form (in which the address is formed by adding the

User’s ManualPPC440x5 CPU Core PreliminaryPage 580 of 583ppc440x5IX.fm.September 12, 2002rlwimi, 399rlwimi., 399rlwinm, 400rlwinm., 400rlwnm, 403rlwnm

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5IX.fm.September 12, 2002Page 581 of 583allocated, 54instructionsall other, exception priorities for,

User’s ManualPPC440x5 CPU Core PreliminaryPage 582 of 583ppc440x5IX.fm.September 12, 2002Decrementer, 191External Input, 185Fixed-Interval Timer, 192F

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5IX.fm.September 12, 2002Page 583 of 583mcrf, 358mcrxr, 359MCSR, 500MCSRR0, 501MCSRR1, 502memory cohe

User’s ManualPPC440x5 CPU Core PreliminaryPage 584 of 583ppc440x5IX.fm.September 12, 2002privileged mode, 80privileged operation, 80privileged SPRs, 8

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5IX.fm.September 12, 2002Page 585 of 583rfi, 167, 397rfmci, 398rlwimi, 399rlwimi., 399rlwinm, 400rlwi

User’s ManualPPC440x5 CPU Core PreliminaryPage 586 of 583ppc440x5IX.fm.September 12, 2002subfze, 434subfze., 434subfzeo, 434subfzeo., 434subi, 258subi

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5IX.fm.September 12, 2002Page 587 of 583U, V, WU0–U3 storage attributes, 147unconditional (UDE) debug

User’s ManualPPC440x5 CPU Core PreliminaryPage 588 of 583ppc440x5IX.fm.September 12, 2002

User’s ManualPreliminary PPC440x5 CPU Corerevlog.fm.September 12, 2002Page 589 of 589Revision LogRevision Date Contents of Modification7/25/2002 Reform

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 59 of 5892.4.1.3 Integer Logical InstructionsTable 2-7 lists the integer

User’s ManualPPC440x5 CPU Core PreliminaryPage 6 of 583ppc440x5TOC.fm.September 12, 20025.1 MMU Overview ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 60 of 589prgmodel.fm.September 12, 20022.4.1.7 Integer Shift InstructionsTable 2-11 lists the integer s

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 61 of 5892.4.3.1 Condition Register Logical InstructionsThese instruction

User’s ManualPPC440x5 CPU Core PreliminaryPage 62 of 589prgmodel.fm.September 12, 2002Table 2-17 shows the processor synchronization instruction in th

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 63 of 5892.4.4.3 Storage Synchronization InstructionsThe storage synchron

User’s ManualPPC440x5 CPU Core PreliminaryPage 64 of 589prgmodel.fm.September 12, 20022.5 Branch ProcessingThe four branch instructions provided by PP

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 65 of 589Table 2-22 summarizes the usage of the bits of the BO field. BO[

User’s ManualPPC440x5 CPU Core PreliminaryPage 66 of 589prgmodel.fm.September 12, 2002The PPC440x5 core combines the static prediction mechanism defin

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 67 of 589When being used as a return address by a bclr instruction, bits

User’s ManualPPC440x5 CPU Core PreliminaryPage 68 of 589prgmodel.fm.September 12, 2002Figure 2-5. Condition Register (CR)0:3 CR0 Condition Register Fi

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 69 of 589Instruction Set on page 249, provides detailed information on ho

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5TOC.fm.September 12, 2002Page 7 of 5836.4.4 Critical Save/Restore Register 0 (CSRR0) ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 70 of 589prgmodel.fm.September 12, 2002• Certain forms of various integer instructions (the “.” forms)

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 71 of 589CR Update By Integer Compare InstructionsInteger compare instruc

User’s ManualPPC440x5 CPU Core PreliminaryPage 72 of 589prgmodel.fm.September 12, 20022.6.2 Integer Exception Register (XER)The XER records overflow a

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 73 of 5892.6.2.1 Summary Overflow (SO) FieldThis field is set to 1 when an

User’s ManualPPC440x5 CPU Core PreliminaryPage 74 of 589prgmodel.fm.September 12, 20022.6.2.2 Overflow (OV) FieldThis field is updated by certain integ

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 75 of 589• Processor Version Register (PVR)Indicates the specific impleme

User’s ManualPPC440x5 CPU Core PreliminaryPage 76 of 589prgmodel.fm.September 12, 20022.7.3 Processor Identification Register (PIR)The PIR is a read-on

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 77 of 589Figure 2-11. Core Configuration Register 0 (CCR0)0 Reserved1 PREP

User’s ManualPPC440x5 CPU Core PreliminaryPage 78 of 589prgmodel.fm.September 12, 20022.7.5 Core Configuration Register 1 (CCR1)Bits 0:19 of CCR1 can c

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 79 of 5892.7.6 Reset Configuration (RSTCFG)The read-only RSTCFG register r

User’s ManualPPC440x5 CPU Core PreliminaryPage 8 of 583ppc440x5TOC.fm.September 12, 20027.4 Watchdog Timer ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 80 of 589prgmodel.fm.September 12, 20022.8 User and Supervisor ModesPowerPC Book-E architecture defines

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 81 of 5892.8.2 Privileged SPRsMost SPRs are privileged. The only defined

User’s ManualPPC440x5 CPU Core PreliminaryPage 82 of 589prgmodel.fm.September 12, 2002The architecture provides two mechanisms for protecting against

User’s ManualPreliminary PPC440x5 CPU Coreprgmodel.fm.September 12, 2002Page 83 of 589XYZ fetch and execute the instruction at address XYZIn this sequ

User’s ManualPPC440x5 CPU Core PreliminaryPage 84 of 589prgmodel.fm.September 12, 2002thought of as being context synchronizing with respect to the MS

User’s ManualPreliminary PPC440x5 CPU Coreinit.fm.September 12, 2002Page 85 of 5893. InitializationThis chapter describes the initial state of the PPC

User’s ManualPPC440x5 CPU Core PreliminaryPage 86 of 589init.fm.September 12, 2002nizing operation (including causing any exceptions which would lead

User’s ManualPreliminary PPC440x5 CPU Coreinit.fm.September 12, 2002Page 87 of 589DBSRUDE 0 Unconditional debug event has not occurredMRR Reset-depend

User’s ManualPPC440x5 CPU Core PreliminaryPage 88 of 589init.fm.September 12, 2002RSTCFGU0 System-dependentAll RSTCFG fields are specified by core inp

User’s ManualPreliminary PPC440x5 CPU Coreinit.fm.September 12, 2002Page 89 of 5893.2 Reset TypesThe PPC440x5 core supports three types of reset: cor

User’s ManualPreliminary PPC440x5 CPU Coreppc440x5TOC.fm.September 12, 2002Page 9 of 5839.3 Pseudocode ...

User’s ManualPPC440x5 CPU Core PreliminaryPage 90 of 589init.fm.September 12, 20022. Invalidate the instruction cache (iccci)3. Invalidate the data ca

User’s ManualPreliminary PPC440x5 CPU Coreinit.fm.September 12, 2002Page 91 of 589care must be taken during the initialization sequence to prevent any

User’s ManualPPC440x5 CPU Core PreliminaryPage 92 of 589init.fm.September 12, 200211. Initialize interrupt resources1. Initialize IVPR to specify high

User’s ManualPreliminary PPC440x5 CPU Coreinit.fm.September 12, 2002Page 93 of 5891. Set MSR[CE] to enable/disable Critical Input and Watchdog Timer i

User’s ManualPPC440x5 CPU Core PreliminaryPage 94 of 589init.fm.September 12, 2002

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 95 of 5894. Instruction and Data CachesThe PPC440x5 core provides separate i

User’s ManualPPC440x5 CPU Core PreliminaryPage 96 of 589cache.fm.September 12, 2002ated with the line that currently resides in that way. The middle-o

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 97 of 589Each of the 16 SPRs illustrated in Figure 4-1 can be written from a

User’s ManualPPC440x5 CPU Core PreliminaryPage 98 of 589cache.fm.September 12, 2002The size of the victim index fields varies according to the size of

User’s ManualPreliminary PPC440x5 CPU Corecache.fm.September 12, 2002Page 99 of 5894.1.2 Cache Locking and Transient MechanismBoth caches support lock