IBM PPC440X5 Manual de usuario descargar pdf (Pagina 285)

100

101

cmpli

Compare Logical Immediate

Preliminary PPC440x5 CPU Core User’s Manual

instrset.fm.

September 12, 2002 Page 285 of 589

cmpli

Compare Logical Immediate

0:3

←

if (RA) (

0 || IM) then c

← 1

if (RA) (

0 || IM) then c

← 1

if (RA) (

0 || IM) then c

← 1

← XER[SO]

← BF

CR[CRn]

← c

0:3

The IM field is extended to 32 bits by concatenating 16 0-bits to its left. The contents of register RA are

compared with IM using a 32-bit unsigned compare.

The CR field specified by the BF field is updated to reflect the results of the compare and the value of

XER[SO] is placed into the same CR field.

Registers Altered

• CR[CRn] where n is speciﬁed by the BF ﬁeld

Invalid Instruction Forms

• Reserved ﬁelds

Programming Note

PowerPC Book-E Architecture defines this instruction as cmpli BF,L,RA,IM, where L selects operand size

for 64-bit implementations. For all 32-bit implementations, L = 0 is required (L = 1 is an invalid form); hence

for the PPC440x5 core, use of the extended mnemonic cmplwi BF,RA,IM is recommended.

cmpli BF, 0, RA, IM

10 BF RA IM

0691116 31

Table 9-14. Extended Mnemonics for cmpli

Mnemonic Operands Function

Other Registers

Changed

cmplwi

[BF,] RA, IM

Compare Logical Word Immediate.

Use CR0 if BF is omitted.

Extended mnemonic for

cmpli BF,0,RA,IM

1 2 ... 280 281 282 283 284 285 286 287 288 289 290 ... 589 590

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