IBM PPC440X5 Manual de usuario Pagina 287
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Valorado. / 5. Basado en revisión del cliente
crand
Condition Register AND
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 287 of 589
crand
Condition Register AND
CR
BT
← CR
BA
∧ CR
BB
The CR bit specified by the BA field is ANDed with the CR bit specified by the BB field; the result is placed
into the CR bit specified by the BT field.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
•CR
BT
Invalid Instruction Forms
• Reserved fields
crand BT, BA, BB
19 BT BA BB 257
0 6 11 16 21 31
- PPC440x5 CPU Core 1
- User’s Manual 1
- Preliminary 1
- Copyright and Disclaimer 2
- Contents 3
- Page 4 of 583 4
- Page 5 of 583 5
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- Page 8 of 583 8
- Page 9 of 583 9
- PPC440x5 CPU Core Preliminary 10
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- Page 22 of 583 22
- About This Book 23
- Notation 24
- Related Publications 25
- Page 26 of 589 26
- 1. Overview 27
- – 64-bit time base 28
- Page 29 of 589 29
- 1.3 PPC440x5 Organization 30
- Page 31 of 589 31
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- 1.4 Core Interfaces 35
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- 2. Programming Model 39
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- 2.2 Registers 47
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- Page 52 of 589 52
- 2.3 Instruction Classes 53
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- .]” syntax 59
- Page 61 of 589 61
- .]” and “[o]” 63
- 2.5 Branch Processing 64
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- 2.6 Integer Processing 71
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- 2.7 Processor Control 74
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- 2.8 User and Supervisor Modes 80
- 2.9 Speculative Accesses 81
- 2.10 Synchronization 82
- Page 83 of 589 83
- Page 84 of 589 84
- 3. Initialization 85
- Page 86 of 589 86
- Page 88 of 589 88
- 3.2 Reset Types 89
- 3.3 Reset Sources 89
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- Page 99 of 589 99
- Page 100 of 589 100
- Preliminary PPC440x5 CPU Core 101
- Page 101 of 589 101
- TRANSIENT LINES 102
- LOCKED LINES 102
- NORMAL LINES 102
- Page 103 of 589 103
- Page 104 of 589 104
- Programming Note: 105
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- 0 Cache line is not valid 113
- 1 Cache line is valid 113
- 0 TID enable 114
- 1 TID disable 114
- 4.3 Data Cache Controller 115
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- 5. Memory Management 133
- Page 134 of 589 134
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- Page 136 of 589 136
- Page 137 of 589 137
- 5.3 Page Identification 138
- Page 139 of 589 139
- 5.4 Address Translation 140
- MSR[IS] for instruction fetch 141
- 5.5 Access Control 142
- Page 143 of 589 143
- Page 144 of 589 144
- 5.6 Storage Attributes 145
- Page 146 of 589 146
- 5.7 Storage Control Registers 147
- Page 148 of 589 148
- Page 149 of 589 149
- Page 150 of 589 150
- 5.8 Shadow TLB Arrays 151
- Page 152 of 589 152
- Page 153 of 589 153
- Page 154 of 589 154
- 5.11 TLB Parity Operations 155
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- Page 158 of 589 158
- 6. Interrupts and Exceptions 159
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- 6.3 Interrupt Processing 162
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- 6.5 Interrupt Definitions 175
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- Machine State Register (MSR) 198
- ME Unchanged 198
- All other MSR bits set to 0 198
- Page 199 of 589 199
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- Page 201 of 589 201
- 6.7 Exception Priorities 202
- Page 203 of 589 203
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- Page 207 of 589 207
- Page 208 of 589 208
- 7.1 Time Base 209
- Page 210 of 589 210
- 7.2 Decrementer (DEC) 211
- Page 212 of 589 212
- 7.4 Watchdog Timer 213
- Page 214 of 589 214
- Page 215 of 589 215
- Page 216 of 589 216
- Page 217 of 589 217
- Page 218 of 589 218
- 8. Debug Facilities 219
- Page 220 of 589 220
- 8.3 Debug Events 221
- IAC Event Enable Field 222
- IAC Mode Field 222
- IAC User/Supervisor Field 223
- Page 224 of 589 224
- Page 225 of 589 225
- DAC Event Enable Field 226
- DAC Mode Field 227
- DAC User/Supervisor Field 228
- DVC Byte Enable Field 228
- Page 229 of 589 229
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- Page 231 of 589 231
- DVC Mode Field 232
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- 8.4 Debug Reset 238
- 8.5 Debug Timer Freeze 238
- 8.6 Debug Registers 238
- 01 Core reset 239
- 01 Reserved 240
- ≤ address < IAC2 241
- ≤ address < IAC4 241
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- 9. Instruction Set 249
- 9.2 Instruction Formats 250
- 9.3 Pseudocode 251
- Page 252 of 589 252
- 9.4 Register Usage 253
- PPC440x5 core 254
- Registers Altered 255
- Add Carrying 256
- Add Extended 257
- Add Immediate 258
- Programming Note 258
- Add Immediate Carrying 259
- Invalid Instruction Forms 262
- AND with Complement 265
- AND Immediate 266
- AND Immediate Shifted 267
- Branch Conditional 270
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- ← CIA + 4 272
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- Page 279 of 589 279
- Page 280 of 589 280
- Page 281 of 589 281
- Programming Notes 284
- Count Leading Zeros Word 286
- Data Cache Block Allocate 295
- Data Cache Block Flush 296
- Exceptions 296
- Data Cache Block Store 298
- Page 301 of 589 301
- Data Cache Block Set to Zero 303
- Page 303 of 589 303
- Architecture Note 304
- Data Cache Read 305
- Divide Word 307
- Divide Word Unsigned 308
- Equivalent 310
- Extend Sign Byte 311
- Extend Sign Halfword 312
- Instruction Cache Block Touch 315
- Page 315 of 589 315
- Instruction Cache Read 317
- Instruction Synchronize 320
- Load Byte and Zero 321
- Load Byte and Zero Indexed 324
- Load Halfword Algebraic 325
- Load Halfword and Zero 330
- Load Multiple Word 334
- Load Word and Reserve Indexed 339
- Load Word and Zero 341
- Load Word and Zero Indexed 344
- Move Condition Register Field 358
- Move From Condition Register 360
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- Page 371 of 589 371
- Page 372 of 589 372
- OR with Complement 393
- OR Immediate 394
- OR Immediate Shifted 395
- Return From Interrupt 397
- Page 401 of 589 401
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- Shift Left Word 405
- Shift Right Word 408
- Store Byte 409
- Store Byte with Update 410
- Store Byte Indexed 412
- Store Halfword 413
- Store Halfword with Update 415
- Store Halfword Indexed 417
- Store Multiple Word 418
- Store Word 422
- Page 425 of 589 425
- Store Word with Update 426
- Store Word Indexed 428
- Subtract From 429
- Subtract From Carrying 430
- Subtract From Extended 431
- TLB Read Entry 435
- Page 435 of 589 435
- TLB Synchronize 438
- Trap Word 441
- Page 441 of 589 441
- Page 442 of 589 442
- Trap Word Immediate 444
- Page 444 of 589 444
- Extended mnemonic for 445
- Invalid Instruction Forms: 446
- XOR Immediate 449
- XOR Immediate Shifted 450
- 10. Register Summary 451
- ICDBDR, ICDBTRH, ICDBTRL 452
- Page 453 of 589 453
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- 10.2 Reserved Fields 457
- 10.3 Device Control Registers 457
- Page 458 of 589 458
- 0.Register Summary 459
- SPR 0x3B3 Supervisor R/W 460
- CCR0 (cont.) 461
- SPR 0x378 Supervisor R/W 462
- CCR1 (cont.) 463
- User Read/Write 464
- SPR 0x03A Supervisor R/W 465
- SPR 0x03B Supervisor R/W 466
- SPR 0x009 User R/W 467
- DAC1–DAC2 468
- SPR 0x134 Supervisor R/W 469
- DBCR0 (cont.) 470
- DBCR1 (cont.) 472
- Debug Control Register 2 473
- Page 473 of 589 473
- DBCR2 (cont.) 474
- SPR 0x3F3 Supervisor R/W 475
- DBSR (cont.) 477
- Page 478 of 589 478
- Page 479 of 589 479
- SPR 0x03D Supervisor R/W 480
- SPR 0x016 Supervisor R/W 481
- Decrementer Auto-Reload 482
- Page 482 of 589 482
- DNV0–DNV3 483
- DTV0–DTV3 484
- DVC1–DVC2 485
- SPR 0x398 Supervisor R/W 486
- SPR 0x03E Supervisor R/W 487
- ESR (cont.) 488
- GPR0–GPR31 489
- IAC1–IAC4 490
- Page 491 of 589 491
- Page 492 of 589 492
- Page 493 of 589 493
- INV0–INV3 494
- ITV0–ITV3 495
- SPR 0x399 Supervisor R/W 496
- IVOR0–IVOR15 497
- SPR 0x03F Supervisor R/W 498
- SPR 0x008 User R/W 499
- Machine Check Status Register 500
- Page 500 of 589 500
- SPR 0x23A Supervisor R/W 501
- SPR 0x23B Supervisor R/W 502
- SPR 0x3B2 Supervisor R/W 503
- Supervisor R/W 504
- MSR (cont.) 505
- SPR 0x030 Supervisor R/W 506
- Page 507 of 589 507
- Processor Version Register 508
- Page 508 of 589 508
- SPR 39B Supervisor Read-Only 509
- SPRG0–SPRG7 510
- SPR 0x01A Supervisor R/W 511
- SPR 0x01B Supervisor R/W 512
- See Time Base on page 209 513
- Timer Control Register 515
- Page 515 of 589 515
- Timer Status Register 516
- Page 516 of 589 516
- SPR 0x100 (User R/W) 517
- Integer Exception Register 518
- Page 518 of 589 518
- A.1 Instruction Formats 519
- A.1.1 Instruction Fields 520
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- A.1.2.5 X-Form 523
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- ←¬((RS) ⊕ (RB)) 538
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- Page 541 of 589 541
- Page 542 of 589 542
- ← (DCR(DCRN)) 543
- ← (MSR) 543
- ← (SPR(SPRN)) 544
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- September 12, 2002 571
- H, I, J, K 578
- Page 588 of 583 588
- Revision Log 589
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