Ibm uPD78082 Manual de usuario Pagina 246
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CHAPTER 16 INSTRUCTION SET
Clock Flag
Note 1 Note 2
ZACCY
CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) ×
CY, sfr.bit 3 – 7 CY ← CY sfr.bit ×
AND1 CY, A.bit 2 4 – CY ← CY A.bit ×
CY, PSW.bit 3 – 7 CY ← CY PSW.bit ×
CY, [HL].bit 2 6 7 CY ← CY (HL).bit ×
CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) ×
CY, sfr.bit 3 – 7 CY ← CY sfr.bit ×
OR1 CY, A.bit 2 4 – CY ← CY A.bit ×
CY, PSW.bit 3 – 7 CY ← CY PSW.bit ×
CY, [HL].bit 2 6 7 CY ← CY (HL).bit ×
CY, saddr.bit 3 6 7 CY ← CY (saddr.bit) ×
CY, sfr.bit 3 – 7 CY ← CY sfr.bit ×
XOR1 CY, A.bit 2 4 – CY ← CY A.bit ×
CY, PSW. bit 3 – 7 CY ← CY PSW.bit ×
CY, [HL].bit 2 6 7 CY ← CY (HL).bit ×
saddr.bit 2 4 6 (saddr.bit) ← 1
sfr.bit 3 – 8 sfr.bit ← 1
SET1 A.bit 2 4 – A.bit ← 1
PSW.bit 2 – 6 PSW.bit ← 1 ×××
[HL].bit 2 6
8
(HL).bit ← 1
saddr.bit 2 4 6 (saddr.bit) ← 0
sfr.bit 3 – 8 sfr.bit ← 0
CLR1 A.bit 2 4 – A.bit ← 0
PSW.bit 2 – 6 PSW.bit ← 0 ×××
[HL].bit 2 6
8
(HL).bit ← 0
SET1 CY 1 2 – CY ← 11
CLR1 CY 1 2 – CY ← 00
NOT1 CY 1 2 – CY ← CY ×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark One instruction clock cycle is one cycle of the CPU clock (f
CPU) selected by the PCC register.
Mnemonic Operands Byte Operation
Instruction
Group
Bit
manipu-
late
- PD78083 1
- SUBSERIES 1
- NOTES FOR CMOS DEVICES 2
- M7 96.5 4
- Regional Information 5
- Other Documents 11
- FIGURE (1/4) 17
- FIGURE (2/4) 18
- FIGURE (3/4) 19
- FIGURE (4/4) 20
- TABLE (1/2) 21
- TABLE (2/2) 22
- CHAPTER 1 OUTLINE 24
- 1.1 Features 24
- 1.2 Applications 25
- 1.3 Ordering Information 25
- 1.4 Quality Grade 26
- DD pin to VDD 27
- SS pin to VSS 27
- SS directly 28
- Pin Identifications 29
- SS via a pull-down resistor 30
- SS : Connect to the ground 30
- DD : Power Supply 31
- PP : Programming Power Supply 31
- SS : Ground 31
- 1.6 78K/0 Series Development 32
- Note 10 bits timer: 1 channel 33
- 1.7 Block Diagram 34
- DD = 1.8 to 5.5 V 35
- A = –40 to +85°C 35
- PD78081(A), 78082(A) and 36
- 78P083(A), and the 36
- PD78081(A2) 36
- CHAPTER 1 OUTLINE 37
- CHAPTER 2 PIN FUNCTION 38
- 2.1 Pin Function List 38
- (2) Pins other than port pins 39
- PD78P083 only) 39
- CHAPTER 2 PIN FUNCTION 40
- As short as possible 44
- CHAPTER 3 CPU ARCHITECTURE 48
- 3.1 Memory Spaces 48
- Figure 3-2. Memory Map ( 49
- PD78082) 49
- Figure 3-3. Memory Map ( 50
- PD78P083) 50
- CHAPTER 3 CPU ARCHITECTURE 52
- PD78081) 53
- IE Z RBS1 AC RBS0 0 ISP CY 56
- PD78081 : 82H 62
- PD78082 : 64H 62
- PD78P083 : 46H 62
- Identifier Description 68
- [Illustration] 72
- — [HL + byte] 74
- — [HL + B], [HL + C] 75
- CHAPTER 4 PORT FUNCTIONS 76
- 4.1 Port Functions 76
- Table 4-1. Port Functions 77
- 4.2 Port Configuration 78
- Internal bus 80
- PM : Port mode register 84
- RD : Port 7 read signal 84
- WR : Port 7 write signal 84
- CHAPTER 4 PORT FUNCTIONS 86
- Input/Output 87
- 4.4 Port Function Operations 90
- CHAPTER 5 CLOCK GENERATOR 92
- CHAPTER 5 CLOCK GENERATOR 94
- 5.4 System Clock Oscillator 96
- (c) Signals are fetched 98
- 5.4.2 Scaler 98
- X) is secured automatically 101
- PM101 : Bit 1 of PM10 106
- 2. n = 5, 6 106
- X = 5.0 MHz 108
- X or fX/2) 109
- Remark n = 5, 6 120
- CHAPTER 7 WATCHDOG TIMER 126
- 7.1 Watchdog Timer Functions 126
- CHAPTER 7 WATCHDOG TIMER 127
- Selector 128
- PCL/P35 Pin Output 134
- CHAPTER 10 A/D CONVERTER 142
- 10.1 A/D Converter Functions 142
- CHAPTER 10 A/D CONVERTER 143
- Tap Selector 143
- REF = VDD 154
- REF and ANI0 to ANI7. Since 155
- REF pin input impedance 155
- REF pin and the AVSS pin 155
- RESET input sets ASIM to 00H 172
- ParityRxD Pin 185
- <3><1> 185
- <2> 185
- WDT : Watchdog timer 205
- CPU: CPU clock) 207
- 1 Instruction 212
- Execution 212
- CHAPTER 13 STANDBY FUNCTION 216
- 13.2.1 HALT mode 218
- Oscillation 220
- DD via a pull-up resistor 221
- CHAPTER 14 RESET FUNCTION 224
- 14.1 Reset Function 224
- CHAPTER 14 RESET FUNCTION 226
- CHAPTER 15 228
- PD78P083 228
- 15.2 PROM Programming 230
- DD = 6.5 V, VPP = 12.5 V 232
- DD = 4.5 to 5.5 V, VPP = VDD 232
- DD and VPP pins 236
- CHAPTER 16 INSTRUCTION SET 238
- CHAPTER 16 INSTRUCTION SET 239
- 16.2 Operation List 241
- Note 1 Note 2 243
- (1) 8-bit instructions 249
- [HL + B] $addr16 250
- [HL + C] 250
- APPENDIX A DEVELOPMENT TOOLS 254
- A.2 PROM Programming Tools 257
- A.3 Debugging Tools 258
- A.3.2 Software (1/3) 259
- S××××SM78K0 259
- A.3.2 Software (2/3) 260
- S××××ID78K0 260
- A.4 OS for IBM PC 262
- Based on EV-9200G-44 264
- (1) Package drawing (in mm) 264
- (2) Pad drawing (in mm) 265
- B.1 Real-time OS 267
- APPENDIX C REGISTER INDEX 270
- C.1 Register Index 270
- APPENDIX C REGISTER INDEX 271
- DD = 1.8 to 5.5V 272
- Facsimile 274
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