Ibm uPD78082 Manual de usuario

µPD78081µPD78081(A)µPD78082µPD78082(A)µPD78P083µPD78P083(A)µPD78P081(A2)µPD78083 SUBSERIES8-BIT SINGLE-CHIP MICROCONTROLLERDocument No. U12176EJ2V0UM0

Development Tool Documents (User’s Manuals)Document nameDocument No.Japanese EnglishRA78K Series Assembler Package Operation EEU-809 EEU-1399Language

77CHAPTER 5 CLOCK GENERATOR5.6 Changing CPU Clock Settings5.6.1 Time required for CPU clock switchoverThe CPU clock can be switched over by means

78CHAPTER 5 CLOCK GENERATOR5.6.2 CPU clock switching procedureThis section describes CPU clock switching procedure.Figure 5-7. CPU Clock Switching(

79CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6The timers incorporated into the µPD78083 subseries are o

80CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 66.1 8-Bit Timer/Event Counters 5 and 6 FunctionsThe 8-bit timer/event counters 5 and 6 (TM5 and TM6)

81CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6(2) External event counterThe number of pulses of an externally input signal can be measured.(3) Squar

82CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 66.2 8-Bit Timer/Event Counters 5 and 6 ConfigurationsThe 8-bit timer/event counters 5 and 6 consist o

83CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6Figure 6-2. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control CircuitNote PM100 : Bi

84CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6(1) Compare registers 50 and 60 (CR50, CR60)These are 8-bit registers to compare the value set to CR50

85CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6Figure 6-3. Timer Clock Select Register 5 FormatNote The timer output (PWM output) cannot be used in

86CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6(2) Timer clock select register 6 (TCL6)This register sets count clocks of 8-bit timer register 6.TCL6

Documents for Embedded Software (User’s Manual)Document nameDocument No.Japanese English78K/0 Series Real-Time OS Basics U11537J —Installation U11536J

87CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6(3) 8-bit timer mode control register 5 (TMC5)This register enables/stops operation of 8-bit timer reg

88CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6(4) 8-bit timer mode control register 6 (TMC6)This register enables/stops operation of 8-bit timer reg

89CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6(5) Port mode register 10 (PM10)This register sets port 10 input/output in 1-bit units.When using the

90CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 66.4 8-Bit Timer/Event Counters 5 and 6 Operations6.4.1 Interval timer operationsBy setting the 8-bit

91CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6Count ClockTMn Count ValueINTTMnTCEnCRn0TOnInterval Time Interval Time Interval TimeInterrupt Request

92CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6Table 6-5. 8-Bit Timer/Event Counters 5 and 6 Interval TimesMinimum Interval Time Maximum Interval Ti

93CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 66.4.2 External event counter operationThe external event counter counts the number of external clock p

94CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 66.4.3 Square-wave outputThis makes the value set in advance in the 8-bit conveyor register 50, 60 (CR

95CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6Table 6-6. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output RangesMinimum Pulse Width Maximum Pu

96CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 66.4.4 PWM output operationsSetting the 8-bit timer mode control registers 5 and 6 (TMC5 and TMC6) as

– i –CONTENTSCHAPTER 1 OUTLINE... 11

97CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6Figure 6-14. PWM Output Operation Timing (Active high setting)Remark n = 5, 6Figure 6-15. PWM Output

98CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6Figure 6-16. PWM Output Operation Timings (CRn0 = FFH, active high setting)Remark n = 5, 6Count Clock

99CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6Figure 6-17. PWM Output Operation Timings (CRn0 changing, active high setting)Caution If CRn0 is chan

100CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 66.5 Cautions on 8-Bit Timer/Event Counters 5 and 6(1) Timer start errorsAn error with a maximum of o

101CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6Count PulseCR50, CR60TM5, TM6 Count ValueX-1 X FFH 00H 01H 02HMN(3) Operation after compare register

102CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6[MEMO]

103CHAPTER 7 WATCHDOG TIMERCHAPTER 7 WATCHDOG TIMER7.1 Watchdog Timer FunctionsThe watchdog timer has the following functions.• Watchdog timer• In

104CHAPTER 7 WATCHDOG TIMER(2) Interval timer modeInterrupt requests are generated at the preset time intervals.Table 7-2. Interval TimesInterval T

105CHAPTER 7 WATCHDOG TIMERPrescalerfXX24fXX25fXX26fXX27fXX28fXX29SelectorWatchdog Timer Mode RegisterInternal BusInternal BusTCL22 TCL21TCL20fXX/23

106CHAPTER 7 WATCHDOG TIMER7.3 Watchdog Timer Control RegistersThe following two types of registers are used to control the watchdog timer.• Timer

– ii –3.2.3 Special Function Register (SFR) ... 373.3 Instructio

107CHAPTER 7 WATCHDOG TIMERFigure 7-2. Timer Clock Select Register 2 FormatTCL277TCL266TCL25 0403210FF42HAddressTCL2SymbolTCL22 TCL21 TCL20500HAft

108CHAPTER 7 WATCHDOG TIMERRUM7060WDTM44WDTM33210FFF9HAddressWDTMSymbol000500HAfterResetR/WR/WRUN01Watchdog Timer Operation Mode SelectionNote 3Coun

109CHAPTER 7 WATCHDOG TIMER7.4 Watchdog Timer Operations7.4.1 Watchdog timer operationWhen bit 4 (WDTM4) of the watchdog timer mode register (WDTM

110CHAPTER 7 WATCHDOG TIMER7.4.2 Interval timer operationThe watchdog timer operates as an interval timer which generates interrupt requests repeat

111CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUITCLOEPCL/P35 Pin Output**CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT8.1 Clock Output Control Circuit FunctionsT

112CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT8.2 Clock Output Control Circuit ConfigurationThe clock output control circuit consists of the following h

113CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT8.3 Clock Output Function Control RegistersThe following two types of registers are used to control the cl

114CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUITPM377PM366PM35 PM344PM333210FF23HAddressPM3SymbolPM32 PM31 PM305FFHAfterResetR/WR/WPM3n01P3n Pin Input/Outp

115CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUITInternal BusfXX/29fXX/210fXX/211TCL27 TCL26 TCL253PM36SelectorTimer Clock Select Register 2Port Mode Regis

116CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT9.3 Buzzer Output Function Control RegistersThe following two types of registers are used to control the

– iii –6.4 8-Bit Timer/Event Counters 5 and 6 Operations ... 906.4.1 Interval timer operation

117CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUITFigure 9-2. Timer Clock Select Register 2 FormatTCL277TCL266TCL25 0403210FF42HAddressTCL2SymbolTCL22 TCL2

118CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUITPM377PM366PM35 PM344PM333210FF23HAddressPM3SymbolPM32 PM31 PM305FFHAfterResetR/WR/WPM3n01P3n Pin Input/Out

119CHAPTER 10 A/D CONVERTERCHAPTER 10 A/D CONVERTER10.1 A/D Converter FunctionsThe A/D converter converts an analog input into a digital value. I

120CHAPTER 10 A/D CONVERTERFigure 10-1. A/D Converter Block DiagramNotes 1. Selector to select the number of channels to be used for analog input.2

121CHAPTER 10 A/D CONVERTER(1) Successive approximation register (SAR)This register compares the analog input voltage value to the voltage tap (comp

122CHAPTER 10 A/D CONVERTER10.3 A/D Converter Control RegistersThe following three types of registers are used to control the A/D converter.• A/D c

123CHAPTER 10 A/D CONVERTERFigure 10-2. A/D Converter Mode Register FormatNotes 1. Set so that the A/D conversion time is 19.1 µs or more.2. Settin

124CHAPTER 10 A/D CONVERTER(2) A/D converter input select register (ADIS)This register determines whether the ANI0/P10 to ANI7/P17 pins should be us

125CHAPTER 10 A/D CONVERTER(3) External interrupt mode register 1 (INTM1)This register sets the valid edge for INTP3.INTM1 is set with an 8-bit memo

126CHAPTER 10 A/D CONVERTER10.4 A/D Converter Operations10.4.1 Basic operations of A/D converter (1) Set the number of analog input channels with

– iv –12.4 Interrupt Servicing Operations ... 18112.4.1 Non-maska

127CHAPTER 10 A/D CONVERTERSARADCRINTADA/D ConverterOperationSampling TimeSampling A/D ConversionConversionTimeUndefined 80HC0Hor 40HConversionResul

128CHAPTER 10 A/D CONVERTER10.4.2 Input voltage and conversion resultsThe relation between the analog input voltage input to the analog input pins

129CHAPTER 10 A/D CONVERTERADM RewriteCS=1, TRG=1StandbyStateANInINTP3A/D ConversionADCRINTADANIn ANIn ANIn ANIm ANImANIn ANInStandbyStateStandbySta

130CHAPTER 10 A/D CONVERTERConversion StartCS=1, TRG=0A/D ConversionADCRINTADANIn ANIn ANImANIn ANIm ANImANInANInADM RewriteCS=1, TRG=0ADM RewriteCS

131CHAPTER 10 A/D CONVERTER10.5 A/D Converter Cautions(1) Power consumption in standby modeThe A/D converter operates on the main system clock. Th

132CHAPTER 10 A/D CONVERTER(3) Noise countermeasuresIn order to maintain 8-bit resolution, attention must be paid to noise on pins AVREF and ANI0 to

133CHAPTER 10 A/D CONVERTERA/D ConversionADCRINTADANIn ANIn ANIm ANImANIn ANIn ANIm ANImADM Rewrite(Start of ANIn Conversion)ADM Rewrite(Start of AN

134CHAPTER 10 A/D CONVERTER[MEMO]

135CHAPTER 11 SERIAL INTERFACE CHANNEL 2CHAPTER 11 SERIAL INTERFACE CHANNEL 211.1 Serial Interface Channel 2 FunctionsSerial interface channel 2 h

136CHAPTER 11 SERIAL INTERFACE CHANNEL 211.2 Serial Interface Channel 2 ConfigurationSerial interface channel 2 consists of the following hardware.

– v –A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 SeriesIn-Circuit Emulator...

137CHAPTER 11 SERIAL INTERFACE CHANNEL 2Internal BusAsynchronousSerial InterfaceMode RegisterAsynchronousSerial InterfaceStatus RegisterReceive Buff

138CHAPTER 11 SERIAL INTERFACE CHANNEL 2TPS3 TPS2 TPS1 TPS0Internal BusMDL3 MDL2 MDL1 MDL0Baud Rate GeneratorControl Register4TXECSIE25-BitCounterSe

139CHAPTER 11 SERIAL INTERFACE CHANNEL 2(1) Transmit shift register (TXS)This register is used to set the transmit data. The data written in TXS is

140CHAPTER 11 SERIAL INTERFACE CHANNEL 211.3 Serial Interface Channel 2 Control RegistersSerial interface channel 2 is controlled by the following

141CHAPTER 11 SERIAL INTERFACE CHANNEL 265432107SymbolASIM TXE RXE PS1 PS0 CL SL ISRM SCKFF70H 00H R/WAddress After Reset

142CHAPTER 11 SERIAL INTERFACE CHANNEL 2Table 11-2. Serial Interface Channel 2 Operating Mode Settings(1) Operation Stop Mode(2) 3-wire Serial I/O

143CHAPTER 11 SERIAL INTERFACE CHANNEL 2PE65432107SymbolASIS 0 0 0 0 0 FE OVEFF71H 00H RAddress After Reset R/WOVE01O

144CHAPTER 11 SERIAL INTERFACE CHANNEL 2Baud Rate Generator Input Clock SelectionMDL3 MDL2 MDL1 MDL0000000001111111100001111000011110011001100110011

145CHAPTER 11 SERIAL INTERFACE CHANNEL 2Figure 11-6. Baud Rate Generator Control Register Format (2/2)5-Bit Counter Source Clock SelectionTPS3 TPS2

146CHAPTER 11 SERIAL INTERFACE CHANNEL 2The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a si

– vi –FIGURE (1/4)Fig. No. Title Page2-1 Pin Input/Output Circuit of List...

147CHAPTER 11 SERIAL INTERFACE CHANNEL 2(b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pinThe transmit/rece

148CHAPTER 11 SERIAL INTERFACE CHANNEL 211.4 Serial Interface Channel 2 OperationSerial interface channel 2 has the following three modes.• Operati

149CHAPTER 11 SERIAL INTERFACE CHANNEL 2SL65432107SymbolASIM TXE RXE PS1 PS0 CL ISRM SCKFF70H 00H R/WAddress After Reset

150CHAPTER 11 SERIAL INTERFACE CHANNEL 265432107SymbolCSIM2 CSIE2 0 0 0 0CSIM22CSCK 0CSCK01Clock Selection in 3-wire Serial I/O ModeInput clock from

151CHAPTER 11 SERIAL INTERFACE CHANNEL 2Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be usedas an inpu

152CHAPTER 11 SERIAL INTERFACE CHANNEL 2PE65432107SymbolASIS 0 0 0 0 0 FE OVEFF71H 00H RAddress After Reset R/WOVE01Ov

153CHAPTER 11 SERIAL INTERFACE CHANNEL 2Baud Rate Generator Input Clock SelectionMDL3 MDL2 MDL1 MDL0000000001111111000011110000111001100110011001010

154CHAPTER 11 SERIAL INTERFACE CHANNEL 25-Bit Counter Source Clock SelectionTPS3 TPS2 TPS1 TPS0 nMCS=1 MCS=00000fXX/210fX/210(4.9 kHz) fX/211(2.4 kH

155CHAPTER 11 SERIAL INTERFACE CHANNEL 2The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, ora sig

156CHAPTER 11 SERIAL INTERFACE CHANNEL 2(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pinThe transmit/rec

– vii –FIGURE (2/4)Fig. No. Title Page6-10 8-Bit Timer Mode Control Register Setting for External Event Counter Operation ... 936-11 Externa

157CHAPTER 11 SERIAL INTERFACE CHANNEL 2(2) Communication operation(a) Data formatThe transmit/receive data format is as shown in Figure 11-7.Figure

158CHAPTER 11 SERIAL INTERFACE CHANNEL 2(b) Parity types and operationThe parity bit is used to detect a bit error in the communication data. Norma

159CHAPTER 11 SERIAL INTERFACE CHANNEL 2D1 D2 D6 D7 ParityD0TxD (Output)INTSTSTOPSTARTD1 D2 D6 D7 ParityD0TxD (Output)INTSTSTOPSTART(c) Transmission

160CHAPTER 11 SERIAL INTERFACE CHANNEL 2D1 D2 D6 D7 ParityD0RxD (Input)INTSRSTOPSTART(d) ReceptionWhen the RXE bit of the asynchronous serial interf

161CHAPTER 11 SERIAL INTERFACE CHANNEL 2(e) Receive errorsThree kinds of errors can occur during a receive operation: a parity error, framing error

162CHAPTER 11 SERIAL INTERFACE CHANNEL 2(3) UART mode cautions(a) In cases where bit 7 (TXE) of the asynchronous serial interface mode register (ASI

163CHAPTER 11 SERIAL INTERFACE CHANNEL 211.4.3 3-wire serial I/O modeThe 3-wire serial I/O mode is useful for connection of peripheral I/Os and dis

164CHAPTER 11 SERIAL INTERFACE CHANNEL 2(b) Asynchronous serial interface mode register (ASIM)ASIM is set with a 1-bit or 8-bit memory manipulation

165CHAPTER 11 SERIAL INTERFACE CHANNEL 2Baud Rate Generator Input Clock SelectionMDL3 MDL2 MDL1 MDL0000000001111111100001111000011110011001100110011

166CHAPTER 11 SERIAL INTERFACE CHANNEL 25-Bit Counter Source Clock SelectionTPS3 TPS2 TPS1 TPS0 nMCS=1 MCS=00000fXX/210fX/210(4.9 kHz) fX/211(2.4 kH

– viii –FIGURE (3/4)Fig. No. Title Page11-6 Baud Rate Generator Control Register Format (2/2) ...

167CHAPTER 11 SERIAL INTERFACE CHANNEL 2When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described bel

168CHAPTER 11 SERIAL INTERFACE CHANNEL 2SI2SCK2 12345678DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0SO2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0SRIFTransfer Start at the

169CHAPTER 11 SERIAL INTERFACE CHANNEL 2Figure 11-13. Circuit of Switching in Transfer Bit OrderStart bit switching is realized by switching the bi

170CHAPTER 11 SERIAL INTERFACE CHANNEL 2[MEMO]

171CHAPTER 12 INTERRUPT FUNCTIONCHAPTER 12 INTERRUPT FUNCTION12.1 Interrupt Function TypesThe following three types of interrupt functions are use

172CHAPTER 12 INTERRUPT FUNCTION12.2 Interrupt Sources and ConfigurationThere are a total of 13 interrupts, combining non-maskable interrupts, mask

173CHAPTER 12 INTERRUPT FUNCTIONInternal BusIE PR ISPMKIFInterruptRequestPriority ControlCircuitVector TableAddressGeneratorStandbyRelease SignalInt

174CHAPTER 12 INTERRUPT FUNCTIONInternal BusPriority ControlCircuitVector TableAddressGeneratorInterruptRequestExternal Interrupt Mode Register(INTM

175CHAPTER 12 INTERRUPT FUNCTION12.3 Interrupt Function Control RegistersThe following five types of registers are used to control the interrupt fu

176CHAPTER 12 INTERRUPT FUNCTIONCautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. Ifa watchdog timer i

NOTES FOR CMOS DEVICES1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORSNote:Strong electric field, when exposed to a MOS device, can cause destruction of th

– ix –FIGURE (4/4)Fig. No. Title Page15-6 PROM Read Timing ...

177CHAPTER 12 INTERRUPT FUNCTIONCautions 1. If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1, MK0 valuebecomes undefined

178CHAPTER 12 INTERRUPT FUNCTIONCautions 1. If a watchdog timer is used in watchdog timer mode 1, set TMPR4 flag to 1.2. Set 1 to the bits 1, 5 to 7

179CHAPTER 12 INTERRUPT FUNCTION(4) External interrupt mode register (INTM0, INTM1)These registers set the valid edge for INTP1 to INTP3.INTM0 and I

180CHAPTER 12 INTERRUPT FUNCTION(5) Program status word (PSW)The program status word is a register to hold the instruction execution result and the

181CHAPTER 12 INTERRUPT FUNCTION12.4 Interrupt Servicing Operations12.4.1 Non-maskable interrupt request acknowledge operationA non-maskable inter

182CHAPTER 12 INTERRUPT FUNCTIONWDTM4=1(with watchdog timermode selected)?Overflow in WDT?WDTM3=0(with non-maskableinterrupt selected)?Interrupt req

183CHAPTER 12 INTERRUPT FUNCTIONFigure 12-10. Non-Maskable Interrupt Request Acknowledge Operation(a) If a new non-maskable interrupt request is ge

184CHAPTER 12 INTERRUPT FUNCTION12.4.2 Maskable interrupt request acknowledge operationA maskable interrupt request becomes acknowledgeable when an

185CHAPTER 12 INTERRUPT FUNCTIONFigure 12-11. Interrupt Request Acknowledge Processing AlgorithmStart× × IF=1?× × MK=0?× × PR=0?AnySimultaneouslyge

186CHAPTER 12 INTERRUPT FUNCTIONFigure 12-12. Interrupt Request Acknowledge Timing (Minimum Time)Remark 1 clock : (fCPU: CPU clock)Figure 12

– x –TABLE (1/2)Table. No. Title Page1-1 Differences between the µPD78081, 78082 and 78P083, the µPD78081(A), 78082(A)and 78P083(A), and the µPD78081

187CHAPTER 12 INTERRUPT FUNCTION12.4.3 Software interrupt request acknowledge operationA software interrupt request is acknowledged by BRK instruct

188CHAPTER 12 INTERRUPT FUNCTIONTable 12-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt ServicingMaskable Interrupt RequestPR

189CHAPTER 12 INTERRUPT FUNCTIONMain Processing INTxxServicingINTyyServicingINTxx(PR=0)1 InstructionExecutionIE=0INTyy(PR=1)EIIE=0EIRETIRETIMain Pro

190CHAPTER 12 INTERRUPT FUNCTIONMain ProcessingINTxxServicingINTyyServicingINTxx(PR=0)1 InstructionExecutionIE=0INTyy(PR=0)IE=0RETIRETIEIFigure 12-1

191CHAPTER 12 INTERRUPT FUNCTION12.4.5 Interrupt request reserveThere are some instructions which, though an interrupt request may be generated whi

192CHAPTER 12 INTERRUPT FUNCTIONThe interrupt request reserve timing is shown in Figure 12-15.Figure 12-15. Interrupt Request HoldRemarks 1. Instru

193CHAPTER 13 STANDBY FUNCTIONCHAPTER 13 STANDBY FUNCTION13.1 Standby Function and Configuration13.1.1 Standby functionThe standby function is d

194CHAPTER 13 STANDBY FUNCTIONAddressFFFAH 04HAfterResetR/WR/W00001Selection of Oscillation StabilizationTime when STOP Mode is Released212/fxx214/f

195CHAPTER 13 STANDBY FUNCTION13.2 Standby Function Operations13.2.1 HALT mode(1) HALT mode set and operating statusThe HALT mode is set by execut

196CHAPTER 13 STANDBY FUNCTIONHALTInstructionWaitStandbyRelease SignalOperatingModeClockHALT Mode WaitOscillationOperating Mode(2) HALT mode clearTh

– xi –TABLE (2/2)Table. No. Title Page12-1 Interrupt Source List ...

197CHAPTER 13 STANDBY FUNCTION(c) Clear upon RESET inputAs is the case with normal reset operation, a program is executed after branch to the reset

198CHAPTER 13 STANDBY FUNCTION13.2.2 STOP mode(1) STOP mode set and operating statusThe STOP mode is set by executing the STOP instruction.Cautions

199CHAPTER 13 STANDBY FUNCTIONSTOPInstructionWait(Time set by OSTS)Oscillation StabilizationWait StatusOperatingModeOscillationOperationgMode STOP M

200CHAPTER 13 STANDBY FUNCTIONRESETSignalOperatingModeClockResetPeriodSTOP ModeOscillation StopOscillation StabilizationWait StatusOperatingModeOsci

201CHAPTER 14 RESET FUNCTIONRESETCount ClockReset Control CircuitWatchdog TimerStopOver-flowResetSignalInterruptFunctionCHAPTER 14 RESET FUNCTION14

202CHAPTER 14 RESET FUNCTIONRESETInternalReset SignalPort PinDelay DelayHi-ZX1Normal OperationReset Period(Oscillation Stop)OscillationStabilizationT

203CHAPTER 14 RESET FUNCTIONTable 14-1. Hardware Status after Reset (1/2)Hardware Status after ResetProgram counter (PC) Note1The contents of reset

204CHAPTER 14 RESET FUNCTIONTable 14-1. Hardware Status after Reset (2/2)Hardware Status after ResetInterrupt Request flag register (IF0L, IF0H, IF1

205CHAPTER 15 µPD78P083CHAPTER 15 µPD78P083The µPD78P083 is a single-chip microcontroller with an on-chip one-time PROM or with an on-chip EPROM wh

206CHAPTER 15 µPD78P083Caution If using mask ROM versions, do not specify any values in the IMS other than when resetting.The IMS settings to give t

– xii –[MEMO]

207CHAPTER 15 µPD78P083RESET VPP VDD CE OE PGM D0-D715.2 PROM ProgrammingThe µPD78P083 incorporate a 24-Kbyte PROM as program memory, respectively.

208CHAPTER 15 µPD78P083(3) Standby modeSetting CE to H sets the standby mode.In this mode, data output becomes high impedance irrespective of the st

209CHAPTER 15 µPD78P08315.2.2 PROM write procedureFigure 15-2. Page Program Mode FlowchartStartAddress = GVDD = 6.5 V, VPP = 12.5 VX = 0LatchAddre

210CHAPTER 15 µPD78P083Figure 15-3. Page Program Mode TimingPage Data LatchPageProgram Program VerifyData Input Data OutputA2-A14A0, A1D0-D7VPPVDDV

211CHAPTER 15 µPD78P083Figure 15-4. Byte Program Mode FlowchartStartAddress = GVDD = 6.5 V, VPP = 12.5 VX = 0X = X + 10.1-ms program pulseVerifyAdd

212CHAPTER 15 µPD78P083Figure 15-5. Byte Program Mode TimingCautions 1. Be sure to apply VDD before applying VPP, and remove it after removing VPP.

213CHAPTER 15 µPD78P08315.2.3 PROM reading procedurePROM contents can be read onto the external data bus (D0 to D7) using the following procedure.(

214CHAPTER 15 µPD78P08315.3 Erasure Procedure (µPD78P083DU Only)With the µPD78P083DU, it is possible to erase ( or set all contents to FFH) the dat

215CHAPTER 16 INSTRUCTION SETCHAPTER 16 INSTRUCTION SETThis chapter describes each instruction set of the µPD78083 subseries as list table. For de

216CHAPTER 16 INSTRUCTION SET16.1 Legends Used in Operation List16.1.1 Operand identifiers and description methodsOperands are described in “Opera

1CHAPTER 1 OUTLINECHAPTER 1 OUTLINE1.1 FeaturesOn-chip ROM and RAMNote The capacities of internal PROM and internal high-speed RAM can be changed

217CHAPTER 16 INSTRUCTION SET16.1.2 Description of “operation” columnA : A register; 8-bit accumulatorX : X registerB : B registerC : C registerD :

218CHAPTER 16 INSTRUCTION SET16.2 Operation ListClock FlagNote 1 Note 2ZACCYr, #byte 2 4 – r ← bytesaddr, #byte 3 6 7 (saddr) ← bytesfr, #byte 3 –

219CHAPTER 16 INSTRUCTION SETClock FlagNote 1 Note 2ZACCYrp, #word 3 6 – rp ← wordsaddrp, #word 4 8 10 (saddrp) ← wordsfrp, #word 4 – 10 sfrp ← word

220CHAPTER 16 INSTRUCTION SETClock FlagNote 1 Note 2ZACCYA, #byte 2 4 – A, CY ← A – byte ×××saddr, #byte 3 6 8 (saddr), CY ← (saddr) – byte ×××A, rN

221CHAPTER 16 INSTRUCTION SETClock FlagNote 1 Note 2ZACCYA, #byte 2 4 – A ← A byte ×saddr, #byte 3 6 8 (saddr) ← (saddr) byte ×A, rNote 324 –A ← A r

222CHAPTER 16 INSTRUCTION SETClock FlagNote 1 Note 2ZACCYADDW AX, #word 3 6 – AX, CY ← AX + word ×××SUBW AX, #word 3 6 – AX, CY ← AX – word ×××CMPW

223CHAPTER 16 INSTRUCTION SETClock FlagNote 1 Note 2ZACCYCY, saddr.bit 3 6 7 CY ← CY (saddr.bit) ×CY, sfr.bit 3 – 7 CY ← CY sfr.bit ×AND1 CY, A.bit

224CHAPTER 16 INSTRUCTION SETClock FlagNote 1 Note 2ZACCY(SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,PC ← addr16, SP ← SP – 2(SP – 1) ← (PC + 2)H, (S

225CHAPTER 16 INSTRUCTION SETClock FlagNote 1 Note 2ZACCYsaddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if(saddr.bit) = 1sfr.bit, $addr16 4 – 11 PC ←

226CHAPTER 16 INSTRUCTION SET16.3 Instructions Listed by Addressing Type(1) 8-bit instructionsMOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MU

2CHAPTER 1 OUTLINE1.2 ApplicationsµPD78081, 78082, 78P083:Airbags, CRT displays, keyboards, air conditioners, hot water dispensers, boilers, fan he

227CHAPTER 16 INSTRUCTION SETSecond Operand[HL + byte]#byte A rNotesfr saddr!addr16PSW [DE] [HL][HL + B] $addr161 NoneFirst Operand[HL + C]A ADD MOV

228CHAPTER 16 INSTRUCTION SET(2) 16-bit instructionsMOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECWSecond OperandFirst OperandAX ADDW MOVW MOVW

229CHAPTER 16 INSTRUCTION SETAX !addr16 !addr11 [addr5] $addr16(4) Call/instructions/branch instructionsCALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT

230CHAPTER 16 INSTRUCTION SET[MEMO]

231APPENDIX A DEVELOPMENT TOOLSAPPENDIX A DEVELOPMENT TOOLSThe following development tools are available for the development of systems which emplo

232APPENDIX A DEVELOPMENT TOOLSFigure A-1. Development Tool ConfigurationEmbedded software• Real-time OS, OS• Fuzzy inference development support

233APPENDIX A DEVELOPMENT TOOLSA.1 Language Processing SoftwareRA78K/0 This assembler converts a program written in mnemonics into an object code e

234APPENDIX A DEVELOPMENT TOOLSA.2 PROM Programming ToolsA.2.1 HardwarePG-1500 This is a PROM programmer capable of programming the single-chip mi

235APPENDIX A DEVELOPMENT TOOLSA.3 Debugging ToolsA.3.1 HardwareIE-78000-R-A This in-circuit emulator helps users in debugging hardware and softwa

236APPENDIX A DEVELOPMENT TOOLSA.3.2 Software (1/3)SM78K0 This simulator can debug target system at C source level or assembler level while simulat

3CHAPTER 1 OUTLINE1.4 Quality GradePart number Package Quality gradeµPD78081CU-××× 42-pin plastic shrink DIP (600 mil) StandardµPD78081GB-×××-3B4 4

237APPENDIX A DEVELOPMENT TOOLSA.3.2 Software (2/3)ID78K0 This is control program that debugs 78K/0 series.Integrated debugger This program employs

238APPENDIX A DEVELOPMENT TOOLSA.3.2 Software (3/3)SD78K/0 This program controls IE-78000-R on host machine with IE-78000-R and host machineScreen

239APPENDIX A DEVELOPMENT TOOLSA.4 OS for IBM PCAs the OS for IBM PC, the following is supported.To run SM78K0, ID78K0, or FE9200 (refer to B.2 Fuz

240APPENDIX A DEVELOPMENT TOOLSA.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit EmulatorIf you already have an

241APPENDIX A DEVELOPMENT TOOLSDrawing and Footprint for Conversion Socket (EV-9200G-44)Figure A-2. EV-9200G-44 Drawing (For Reference Only)AFD1EEV

242APPENDIX A DEVELOPMENT TOOLSFigure A-3. EV-9200G-44 Footprint (For Reference Only)0.031 × 0.394=0.3150.031 × 0.394=0.315AFDEBGHIJC

243APPENDIX B EMBEDDED SOFTWAREAPPENDIX B EMBEDDED SOFTWAREThis section describes the embedded software which are provided for the µPD78083 sub

244APPENDIX B EMBEDDED SOFTWAREB.1 Real-time OSMX78K0µITRON-specification subset OS. Nucleus of MX78K0 is supplied.OS This OS performs task man

245APPENDIX B EMBEDDED SOFTWAREB.2 Fuzzy Inference Development Support SystemFE9000/FE9200 This program supports input of fuzzy knowledge data (

246APPENDIX B EMBEDDED SOFTWARE[MEMO]

4CHAPTER 1 OUTLINE1.5 Pin Configuration (Top View)(1) Normal operating mode42-pin plastic shrink DIP (600 mil)µPD78081CU-×××, 78082CU-×××, 78P083CU

247APPENDIX C REGISTER INDEXAPPENDIX C REGISTER INDEXC.1 Register Index8-bit timer mode control register (TMC5)...

248APPENDIX C REGISTER INDEX[P]P0: Port0 ...

249APPENDIX D REVISION HISTORYAPPENDIX D REVISION HISTORYMajor revisions by edition and revised chapters are shown below.Edition Major revisions

250APPENDIX D REVISION HISTORYEdition Major revisions from previous version Revised Chapter2nd Figure A-1. Development Tool Configuration has been

Although NEC has taken all possible stepsto ensure that the documentation suppliedto our customers is complete, bug freeand up-to-date, we readily acc

5CHAPTER 1 OUTLINE• 44-pin plastic QFP (10 × 10 mm)µPD78081GB-×××-3B4, 78081GB-×××-3BS-MTXµPD78082GB-×××-3B4, 78082GB-×××-3BS-MTXµPD78P083GB-3B4, 78

6CHAPTER 1 OUTLINEPin IdentificationsANI0 to ANI7 : Analog Input P100, P101 : Port 10ASCK : Asynchronous Serial Clock PCL : Programmable ClockAVDD :

FIP, IEBus, and QTOP are trademarks of NEC Corporation.MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in t

7CHAPTER 1 OUTLINE(2) PROM programming mode• 42-pin plastic shrink DIP (600 mil)µPD78P083CU, 78P083CU(A)• 42-pin ceramic shrink DIP (with window) (6

8CHAPTER 1 OUTLINENote Under developmentCautions 1. (L) : Connect individually to VSS via a pull-down resistor.2. VSS : Connect to the ground.3. RES

9CHAPTER 1 OUTLINE1.6 78K/0 Series DevelopmentThe following shows the 78K/0 Series products development. Subseries names are shown inside frames.N

10CHAPTER 1 OUTLINEThe following table shows the differences among subseries functions.Function ROM Timer 8-bit10-bit8-bitSerial interface I/OExtern

11CHAPTER 1 OUTLINE1.7 Block DiagramRemarks 1. The internal ROM and high-speed RAM capacities depend on the product.2. Pin connection in parenthese

12CHAPTER 1 OUTLINE1.8 Outline of FunctionPart NumberµPD78081µPD78082µPD78083ItemInternal memory ROM Mask ROM PROM8 Kbytes 16 Kbytes 24 KbytesNoteH

13CHAPTER 1 OUTLINE1.9 Differences between the µPD78081, 78082 and 78P083, the µPD78081(A), 78082(A) and78P083(A), and the µPD78081(A2)Table 1-1 Di

14CHAPTER 1 OUTLINE[MEMO]

15CHAPTER 2 PIN FUNCTIONCHAPTER 2 PIN FUNCTION2.1 Pin Function List2.1.1 Normal operating mode pins(1) Port pinsNote When P10/ANI0-P17/ANI7 pins

16CHAPTER 2 PIN FUNCTIONPin Name Input/Output Function After Reset Alternate FunctionINTP1 Input External interrupt request input by which the activ

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.The information in this documen

17CHAPTER 2 PIN FUNCTION2.2 Description of Pin Functions2.2.1 P00 to P03 (Port 0)These are 4-bit input/output ports. Besides serving as input/out

18CHAPTER 2 PIN FUNCTION2.2.3 P30 to P37 (Port 3)These are 8-bit input/output ports. Beside serving as input/output ports, they function as clock

19CHAPTER 2 PIN FUNCTION2.2.5 P70 to P72 (Port 7)This is a 3-bit input/output port. In addition to its use as an input/output port, it also has se

20CHAPTER 2 PIN FUNCTION2.2.7 AVREFA/D converter reference voltage input pin.When A/D converter is not used, connect this pin to VSS.2.2.8 AVDDAna

21CHAPTER 2 PIN FUNCTION2.2.15 IC (Mask ROM version only)The IC (Internally Connected) pin is provided to set the test mode to check the µPD78083 S

22CHAPTER 2 PIN FUNCTIONPin Name Input/Output Input/Output Recommended Connection for Unused PinsCircuit TypeP00 2 Input Connect to VSS.P01/INTP1 8-

23CHAPTER 2 PIN FUNCTIONFigure 2-1. Pin Input/Output Circuit of ListINpull-upenableVDDP-chIN/OUTinputenableoutputdisabledataVDDP-chN-chType 2Type 5

24CHAPTER 2 PIN FUNCTION[MEMO]

25CHAPTER 3 CPU ARCHITECTURECHAPTER 3 CPU ARCHITECTURE3.1 Memory SpacesFigures 3-1 to 3-3 shows memory maps.Figure 3-1. Memory Map (µPD78081)Data

26CHAPTER 3 CPU ARCHITECTUREFigure 3-2. Memory Map (µPD78082)Data memory spaceGeneral Registers32 × 8 bitsInternal ROM16384 × 8 bitsCALLF Entry Are

NEC Electronics Inc. (U.S.)Santa Clara, CaliforniaTel: 800-366-9782Fax: 800-729-9288NEC Electronics (Germany) GmbHDuesseldorf, GermanyTel: 0211-65 03

27CHAPTER 3 CPU ARCHITECTUREFigure 3-3. Memory Map (µPD78P083)Data memory spaceGeneral Registers32 × 8 bitsInternal PROM24576 × 8 bitsCALLF Entry A

28CHAPTER 3 CPU ARCHITECTURE3.1.1 Internal program memory spaceThe internal program memory is mask ROM with a 8192 × 8-bit configuration in the µPD

29CHAPTER 3 CPU ARCHITECTURE3.1.2 Internal data memory spaceThe internal high speed RAM configuration is 256 × 8-bit in the µPD78081, 384 × 8-bit i

30CHAPTER 3 CPU ARCHITECTUREFigure 3-4. Data Memory Addressing (µPD78081)General Registers32 × 8 bitsInternal ROM8192 × 8 bitsUnusableInternal High

31CHAPTER 3 CPU ARCHITECTUREFigure 3-5. Data Memory Addressing (µPD78082)General Registers32 × 8 bitsInternal ROM16384 × 8 bitsUnusableInternal Hig

32CHAPTER 3 CPU ARCHITECTUREFigure 3-6. Data Memory Addressing (µPD78P083)General Registers32 × 8 bitsInternal PROM24576 × 8 bitsUnusableInternal H

33CHAPTER 3 CPU ARCHITECTURE70IE Z RBS1 AC RBS0 0 ISP CYPC15 03.2 Processor RegistersThe µPD78083 subseries units incorporate the following process

34CHAPTER 3 CPU ARCHITECTURE(a) Interrupt enable flag (IE)This flag controls the interrupt request acknowledge operations of the CPU.When IE = 0, al

35CHAPTER 3 CPU ARCHITECTURERETI and RETB InstructionPSWPC15-PC8PC15-PC8PC7-PC0Register Pair LowerSP SP + 2SPRegister Pair UpperRET InstructionP

36CHAPTER 3 CPU ARCHITECTUREBANK0BANK1BANK2BANK3FEFFHFEF8HFEE0HHLDEBCAXH15 0 7 0LDEBCAX16-Bit Processing 8-Bit ProcessingFEF0HFEE8HBANK0BANK1BANK2BA

Major Revision in This EditionPage DescriptionThroughout The following products have been already developedµPD78081CU-×××, 78081GB-×××-3B4, 78082CU-××

37CHAPTER 3 CPU ARCHITECTURE3.2.3 Special Function Register (SFR)Unlike a general register, each special-function register has special functions.It

38CHAPTER 3 CPU ARCHITECTUREAddress Special-Function Register (SFR) Name Symbol R/W After ResetFF00H Port0 P0 R/W √√— 00HFF01H Port1 P1 √√—FF03H Por

39CHAPTER 3 CPU ARCHITECTUREAddress Special-Function Register (SFR) Name Symbol R/W After ResetFFEAH Priority order specify flag register 1L PR1L R/

40CHAPTER 3 CPU ARCHITECTURE15 0PC+15 0876S15 0PCαjdisp8When S = 0, all bits of α are 0.When S = 1, all bits of α are 1.PC indicates the start addre

41CHAPTER 3 CPU ARCHITECTURE3.3.2 Immediate addressing[Function]Immediate data in the instruction word is transferred to the program counter (PC) a

42CHAPTER 3 CPU ARCHITECTURE3.3.3 Table indirect addressing[Function]Table contents (branch destination address) of the particular location to be a

43CHAPTER 3 CPU ARCHITECTURE70rp07AX15 0PC873.3.4 Register addressing[Function]Register pair (AX) contents to be specified with an instruction word

44CHAPTER 3 CPU ARCHITECTURE3.4 Operand Address AddressingThe following various methods are available to specify the register and memory (addressin

45CHAPTER 3 CPU ARCHITECTURE3.4.2 Register addressing[Function]This addressing accesses a general register as an operand. The general register acc

46CHAPTER 3 CPU ARCHITECTURE3.4.3 Direct addressing[Function]This addressing directly addresses the memory indicated by the immediate data in an in

PREFACEReaders This manual has been prepared for user engineers who want to understand thefunctions of the µPD78083 subseries and design and develop i

47CHAPTER 3 CPU ARCHITECTURE3.4.4 Short direct addressing[Function]The memory to be manipulated in the fixed space is directly addressed with 8-bit

48CHAPTER 3 CPU ARCHITECTURE150Short Direct MemoryEffective Address11111118707OP codesaddr-offsetα[Description example]MOV 0FE30H, #50H; when setti

49CHAPTER 3 CPU ARCHITECTURE150SFREffective Address11111118707OP codesfr-offset13.4.5 Special-Function Register (SFR) addressing[Function]The memor

50CHAPTER 3 CPU ARCHITECTURE3.4.6 Register indirect addressing[Function]This addressing addresses the memory with the contents of a register pair s

51CHAPTER 3 CPU ARCHITECTURE3.4.7 Based addressing[Function]This addressing addresses the memory by adding 8-bit immediate data to the contents of

52CHAPTER 3 CPU ARCHITECTURE3.4.8 Based indexed addressing[Function]This addressing addresses the memory by adding the contents of the HL register,

53CHAPTER 4 PORT FUNCTIONSCHAPTER 4 PORT FUNCTIONS4.1 Port FunctionsThe µPD78083 Subseries units incorporate an input port and thirty-two input/ou

54CHAPTER 4 PORT FUNCTIONSPin Name Input/Output Function Dual-Function PinP00 Input Port 0 Input only —P01 Input/output 4-bit input/output port Inpu

55CHAPTER 4 PORT FUNCTIONS4.2 Port ConfigurationA port consists of the following hardware:Table 4-2. Port Configuration I

56CHAPTER 4 PORT FUNCTIONSFigure 4-2. P00 Block DiagramFigure 4-3. P01 to P03 Block DiagramPUO : Pull-up resistor option registerPM : Port mode

To know application examples of the functions provided in the µPD78083 Subseries:→ Refer to Application Note separately provided.Legend Data represent

57CHAPTER 4 PORT FUNCTIONS4.2.2 Port 1Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit u

58CHAPTER 4 PORT FUNCTIONS4.2.3 Port 3Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mo

59CHAPTER 4 PORT FUNCTIONS4.2.4 Port 5Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mo

60CHAPTER 4 PORT FUNCTIONS4.2.5 Port 7This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by m

61CHAPTER 4 PORT FUNCTIONSFigure 4-8. P71 and P72 Block DiagramPUO : Pull-up resistor option registerPM : Port mode registerRD : Port 7 read sig

62CHAPTER 4 PORT FUNCTIONS4.2.6 Port 10This is an 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by

63CHAPTER 4 PORT FUNCTIONS4.3 Port Function Control RegistersThe following two types of registers control the ports.• Port mode registers (PM0, PM1

64CHAPTER 4 PORT FUNCTIONSTable 4-3. Port Mode Register and Output Latch Settings when Using Dual-FunctionsP01 to P03 INTP1 to INTP3 Input 1 ×P10 t

65CHAPTER 4 PORT FUNCTIONSFigure 4-10. Port Mode Register FormatPM0PM11 1 PM03 PM02 PM01 176543210SymbolPM3PM5FF20HFF21HFF23HFF25HFFHFFHFFHFFHR/WR/

66CHAPTER 4 PORT FUNCTIONS(2) Pull-up resistor option register (PUOH, PUOL)This register is used to set whether to use an internal pull-up resistor

Related Documents The related documents indicated in this publication may include preliminaryversions. However, preliminary versions are not marked a

67CHAPTER 4 PORT FUNCTIONS4.4 Port Function OperationsPort operations differ depending on whether the input or output mode is set, as shown below.4

68CHAPTER 4 PORT FUNCTIONS[MEMO]

69CHAPTER 5 CLOCK GENERATORCHAPTER 5 CLOCK GENERATOR5.1 Clock Generator FunctionsThe clock generator generates the clock to be supplied to the CPU

70CHAPTER 5 CLOCK GENERATORFigure 5-1. Block Diagram of Clock GeneratorMain SystemClock OscillatorX2X1STOPPCC2PCC1Internal BusStandby Control Circu

71CHAPTER 5 CLOCK GENERATOR5.3 Clock Generator Control RegisterThe clock generator is controlled by the following two registers:• Processor clock c

72CHAPTER 5 CLOCK GENERATORWrite to OSMS(MCS 0)fXXMax. 2/fXOperating at fXX = fX/2 (MCS = 0) Operating at fXX = fX/2 (MCS = 0)MCSMain System Clock

73CHAPTER 5 CLOCK GENERATOR5.4 System Clock Oscillator5.4.1 Main system clock oscillatorThe main system clock oscillator oscillates with a crystal

74CHAPTER 5 CLOCK GENERATORFigure 5-6. Examples of Oscillator with Bad Connection (1/2)(a) Wiring of connection circuits (b) Signal conductors inte

75CHAPTER 5 CLOCK GENERATOR Figure 5-6. Examples of Oscillator with Bad Connection (2/2)(c) Signals are fetched5.4.2 ScalerThe scaler divides the

76CHAPTER 5 CLOCK GENERATOR5.5 Clock Generator OperationsThe clock generator generates the following various types of clocks and controls the CPU o